This paper presents a methodology for generating floatingpoint arithmetic hardware designs which are, for suitable applications, dramatically reduced in size, while still retaining performance. We use a profiling tool for floating-point value ranges to identify arithmetic operations where the shifting required for alignment and normalisation is almost always small. We synthesise hardware with r...

Semiconductor companies have increasingly adopted a methodology that starts with a system-level design specification in C/C++/SystemC. This model is extensively simulated to ensure correct functionality and performance. Later, a Register Transfer Level (RTL) implementation is created in Verilog, either manually by a designer or automatically by a high-level synthesis tool. It is essential to ch...

Matrix inversion is widely used in numerous signal processing and data analysis algorithms. Many of these algorithms use a floating-point data format to accommodate large dynamic ranges of the random matrices (see Adaptive Beamforming for Radar: Floating-Point QRD+WBS in an FPGA (WP452) [Ref 1]). This application note focuses on the design of a scalable matrix inversion function using the Vivad...

In this paper, generation-type drain current transients, in advanced (down to 50nm gate-length) floating-body PD SOI MOSFETs are investigated by 2D numerical simulation in weak inversion operation. An original compact analytical model is derived for the pure transient weak inversion operation and validated on both elementary and realistic 2D structures. The proposed sub-threshold transient comp...

this study was performed to design bilayer regioselective floating tablets of atenolol and lovastatin to give immediate release of lovastatin and sustained release of atenolol. bilayer floating tablets comprised two layers, i.e immediate release and controlled release layers. the immediate release layer comprised sodium starch glycollate as a super disintegrant and the sustained release layer c...

21  AbstractThis paper concentrates on the FPGA implementation of discrete Fourier transforms (DFT) and inverse discrete Fourier transform (IDFT) based on floating point numbers. Floating point representation of the numbers support much wider range of values and achieve greater range at the expense of precision. Firstly general purpose arithmetic modules addition, subtraction, multiplier and d...

This paper presents a methodology for generating floatingpoint arithmetic hardware designs which are, for suitable applications, dramatically reduced in size, while still retaining performance. We use a profiling tool for floating-point value ranges to identify arithmetic operations where the shifting required for operand alignment is almost always small. We synthesise hardware with reduced-siz...

Carvedilol (CVD) is an antihypertensive agent with a short half-life, pH-dependent solubility, and narrow absorption window. The purpose of this research was to prepare a floating-drug delivery-system of carvedilol to increase its half-life. The present study investigates the preparation of carvedilol-floating microspheres, evaluates the floating-drug delivery-system (FDDS) (by scanning electro...