the critical charge by increasing the gate capacitance while errors are gaining importance as technology scales. Flip-flops, an important component of pipelined architectures, are becoming more susceptible to soft errors. This work analyzes soft error rates on a variety of flip-flops. The analysis was performed by implementing and simulating the various designs in 70 nm, 1V CMOS technology. Fir...

This paper describes two approaches that allow us to intersect rays with triangular meshes more quickly by amortizing computation over neighbouring triangles. The first approach accomplishes this by performing the in-out test for each triangle using three plane equations, each one representing a boundary edge for the triangle. Each plane is shared between four neighbouring triangles and the cos...

Multi-threshold voltage CMOS (MTCMOS) is an effective technique for suppressing the leakage currents in idle circuits. When the conventional MTCMOS technique is directly applied to a sequential circuit however the stored data is lost during the low-leakage sleep mode. Significant energy and timing penalties are suffered to restore the pre-sleep system state at the end of the sleep mode with the...

Prior to computing the Cholesky factorization of a sparse, symmetric positive definite matrix, a reordering of the rows and columns is computed so as to reduce both the number of fill elements in Cholesky factor and the number of arithmetic operations (FLOPs) in the numerical factorization. These two metrics are clearly somehow related and yet it is suspected that these two problems are differe...

In this short note, we are concerned with the evaluation of certain convolution integrals with singular kernels. The problem is as follows. Given a kernel function K(t) which is very often singular at the origin and a density function σ(t), evaluate C(t) = ∫ t 0 K(t − τ)σ(τ)dτ for t = ∆t, 2∆t, · · · , T = N∆t. We will oftern write C(tk) = C(k∆t) = Ck in short, and similarly for σ. Direct comput...

Data-driven clock gating is reducing the total power consumption of VLSI chips. There, flip-flops are merged and share a common clock signal. Finding the optimal clusters is the key for maximizing the power savings. To reduce the hardware overhead involved, flip-flops (FFs) are merged so that they share a common clock enabling signal. Power optimization system to decrease clock power by using M...

A new partial BIST insertion approach based on eliminating data correlation to improve pseudo-random testability is presented. Data correlation causes the circuit to be in a subset of the states more or less frequently, which leads to low fault coverage in pseudo-random test. One important cause of correlation is reconvergent fanout. Incorporating BIST test flip-flops into reconvergent paths wi...