In hardware security and trusted computing it is often desired to uniquely and unambiguously identify a device among several others of the same brand. Physically unclonable functions (PUFs) take advantage of subtle variations in the devices’ production process to achieve this. A ring oscillator (RO) PUF exploits differing time delays of circuits to yield a unique response from each device. The ...

In order to enable efficient integration of FPGAs into cost effective and reliable high-performance systems as well potentially into low power mobile systems, their power efficiency needs to be improved. In this paper, we propose a power management scheme for FPGAs centered on a power-driven partitioning technique. Our power-driven partitioner creates clusters within a design such that within i...

A major focus within the Integrated Chip (IC) industry is reducing power consumption of devices. In this paper, we explore the idea of persistent CAD algorithms that constantly improve the power consumption of consumer devices that use FPGAs. The idea is that the field-programmability of an FPGA allows updates to be deployed in the field, and as CAD algorithms find optimizations for a design, t...

As technology scales down, dense integration and high operating frequencies associated with increased number of I/O buffers are factors contributing to electromagnetic emission (EME) increase FPGA devices. Noting that the EME depends not only on dynamic power dissipated by device, but also coupling degree between layout routed tracks signal switching activity along these tracks, it is interest ...

Configurable systems offer a unique opportunity to define application-specific architectures. These architectures offer performance advantages, where the use of customized pipelines exploits the inherent parallelism of the application. In this research, we describe a set of program analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined imp...

From silicon to science : the long road to production reconfigurable supercomputing p. 2 The von Neumann syndrome and the CS education dilemma p. 3 Optimal unroll factor for reconfigurable architectures p. 4 Programming reconfigurable decoupled application control accelerator for mobile systems p. 15 DNA physical mapping on a reconfigurable platform p. 27 Hardware BLAST algorithms with multi-se...

This work aims to introduce a design methodology of Time-to-Digital Converters (TDCs) on low cost Field-Programmable Gate Array (FPGA) targets. First, the paper illustrates how to take advantage of the presence of carry chains in elementary logic elements of the FPGA in order to enhance the TDC resolution. Then, it describes how to use the Chip Planner tool to place the partitions composing the...

We examine empirically the performance of multi-level logic minimization tools for a lookup table-based Field-Programmable Gate Array (FPGA) technology. The experiments are conducted by using the university tools misII for combinational logic minimization and mustang for state assignment, and the industrial tools xnfmap for technology mapping and apr for automatic placement and routing. We meas...

results the mean distances between the crestal bone and the implant shoulder in group 1 were 1.01, 1.44, and 1.93 mm at the implant placement time, and at the 6 and 12-month postoperative intervals, respectively. in group 2, these distances were 1.35, 1.20, and 1.41 mm, respectively. there were no significant differences in the marginal bone resorption between the two groups (p > 0.05). conclus...