As the scaling of MOSFETs continues the requirement to maintain electrostatic integrity dictates an aggressive reduction of the oxide thickness below 1 nm, introducing intolerably high gate leakage [1]. This has led to the introduction of high-κ materials in the gate stack offering the required SiO2 equivalent oxide thickness at increased physical thickness and reduced gate leakage. There are m...

There is broad interest in surface functionalization of 2D materials and its related applications. In this work, we present a novel graphene layer transistor fabricated by introducing fluorinated graphene (fluorographene), one of the thinnest 2D insulator, as the gate dielectric material. For the first time, the dielectric properties of fluorographene, including its dielectric constant, frequen...

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities ( gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is obs...

This study investigates geometrical variability on the sensitivity of the junctionless tunneling field effect transistor (JLTFET) and Heterostructure JLTFET (HJLTFET) performance. We consider the transistor gate dielectric thickness as one of the main variation sources. The impacts of variations on the analog and digital performance of the devices are calculated by using computer aided design (...

We propose a novel sloped dielectric geometry in graphene as a band engineering method for widening the depletion region and increasing the electrical rectification effect in graphene pn junctions. Enhanced current-rectification was achieved in a bilayer graphene with a sloped dielectric top gate and a normal back gate. A bias was applied to the top gate to induce a spatially modulated and slop...

We have studied parylene-N and parylene-C for their use as substrates and gate dielectrics in OTFTs. Parylene-N films with a thickness of 300 nm show the required dielectric properties, as verified by breakthrough-voltage measurements. The surface roughness measured for 300 nm thick parylene-N films is 4–5 nm. However, initial growth of parylene depends on the subjacent surface. This results in...

Yang, Tian M.S.E.C.E, Purdue University, December, 2007. Capacitance-voltage studies of atomic-layer-deposited MOS structrures on Gallium Arsenide and other III-V compound semiconductors . Major Professor: Peide Ye. Si-based CMOS devices with traditional structure are approaching the fundamental physical limits. New device structures and materials must be explored to continue the trend of incre...