As the semiconductor industry is moving to more advanced technology nodes, simple scaling of device dimensions and voltages, which worked so well for many decades, is no longer sufficient to continue improving circuit performance. New materials are being introduced and the existing ones are modified to optimize their properties. High dielectric constant (high k) insulators are being developed a...

In this paper various mixers are defined for CDMA applications . Using CMOS makes easier for mixers to act on same chip with other digital and analog circuits . The topologies we are defining are dual gate mixers , back gate mixers, single balanced current switching mixers and back end mixers . The backgate mixer utilizes the inherent lateral bipolar transistor in CMOS. Device simulations were ...

We used an ensemble Monte Carlo simulator to study both the dc and transient behavior of a double gate silicon-on-insulator transistor sDGSOId operated as a velocity modulation transistor sVMTd and as a conventional field effect transistor sFETd. Operated as a VMT, the DGSOI transistor provides switching times shorter than 1 ps regardless of the channel length, with a significant current modula...

In this paper the performance of 8-transistor based Full adder is analyzed, evaluated, and compared with that of three different types of Full Adders based on Complementary Pass Transistor XOR Logic gate. Simulation results using nano-scale SPICE parameters are obtained for the above mentioned FAs. It is shown that the performance of the 8-transistor based Full adder in term of power dissipatio...

In this paper, a new high-speed circuit technique called differential cascode voltage switch with pass-gate (DCVSPG) logic tree is presented. The circuit technique is designed using a pass-gate logic tree in DCVSPG instead of the nMOS logic tree in the conventional DCVS circuit, which eliminates the floating node problem. By eliminating the floating node problem, the DCVSPG becomes a new type o...

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical...

In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing as to guarantee synchronously arriving signal slopes at the input of logic gates, thereby avoiding glitches. Since the delay of logic gates depends directly on transistor sizes, their variation allows to equalize different path delays without influencing the total delay of the circuit. Unfortuna...

This paper introduces future devices for multi-valued logic implementation. Quantum dot gate field effect transistor (QDGFET) works based on the change in threshold voltage due to stored charge in the quantum dots in the gate region. Quantum dot channel field effect transistor (QDCFET) produces more number of states in their transfer characteristics because of charge flow through the mini-band ...

A linear stacked field-effect transistor (FET) power amplifier (PA) is implemented using a 0.18-μm silicon-on-insulator CMOS process for W-CDMA handset applications. Phase distortion by the nonlinear gate-source capacitance (Cgs) of the common-source transistor, which is one of the major nonlinear sources for intermodulation distortion, is compensated by employing a PMOS linearizer with improve...

Bradley A. Minch, Chris Diorio, Paul Hasler, Carver Mead Computation and Neural Systems California Institute of Technology Pasadena, CA 91125 (818) 395-6996 [email protected] ABSTRACT In this paper, we describe a novel circuit consisting of N + 1 MOS transistors and a single oating gate which computes a soft maximumof N current inputs and re ects the result in the output transistor. An in...