Gain Clamped Semiconductor Optical Amplifier (GC-SOA), All Optical flip flop (AOff), Distributed bragg reflector (DBR), bistability property ABSTRACT In this article, the effect of coupling coefficient variations on an all optical Flip Flop performance based on gain clamped semiconductor optical amplifier according to distributed bragg reflectors by extensive band model of wave diffusion in tim...

The flip and flop splice variants of AMPA receptors show strikingly different sensitivity to allosteric regulation by cyclothiazide; heteromers assembled from GluR-A and GluR-B also exhibit splice variant-dependent differences in efficacy for activation by glutamate and kainate. The sensitivity for attenuation of desensitization by cyclothiazide for homomeric GluR-A was solely dependent upon ex...

In our previous work we proposed a Multilayer Perceptron Neural Networks (MLP NN) consisting of fuzzy flipflops (F3) based on various operations. We showed that such kind of fuzzy-neural network had good learning properties. In this paper we propose an evolutionary approach for optimizing fuzzy flip-flop networks (FNN). Various popular fuzzy operation and three different fuzzy flip-flop types w...

The dynamics of the flip-flop motion of single buckled dimers of Si(100) was elucidated by locating the tip of a scanning tunneling microscope over a single flip-flopping dimer and measuring the tunneling current (time trace). Based on a statistical analysis of the time trace, we succeeded in estimating the activation energy and the energy splitting between the two stable configurations of buck...

Submitted: Jan 13, 2013; Accepted: Feb 26, 2013; Published: Aug 18, 2013 Abstract: This paper presents the design and performance evaluation of a modified complementary energy path adiabatic logic (MCEPAL) circuit. A simulative investigation on the proposed MCEPAL based, multiplexer, JK flip flop and 3 bit counter has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technolog...

The clock distribution network in digital integrated circuits distributes the clock signal which acts as a timing reference controlling data flow within the system. Since the clock signal has highest capacitance and operates at high frequencies, the clock distribution network consumes a large amount of total power in synchronous system. So, a new flip-flop is proposed in a low-swing resonant cl...

In this paper, we propose a new architecture of non-volatile Flip-Flop based on ReRAM unipolar resistive memory element (RNVFF). This architecture is proposed in the context of power-down applications. Flip-Flop content is saved into ReRAM memory cell before power-down and restored after power-up. To simulate such a structure a compact model of unipolar ReRAM was developed and calibrated on bes...

In this paper, a low power implicit type pulsed flip-flop (PFF) using self-driven pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. The pass transistor logic driven by generated clock pulse is used directly to drive the output of the flip-flop. The proposed de...

The AMPA-type glutamate receptor (AMPAR) subunit composition shapes synaptic transmission and varies throughout development and in response to different input patterns. Here, we show that chronic activity deprivation gives rise to synaptic AMPAR responses with enhanced fidelity. Extrasynaptic AMPARs exhibited changes in kinetics and pharmacology associated with splicing of the alternative flip/...

Practically, clocking system like flip-flop (FF) consumes large portion of total chip power. In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. Pulsetriggered FF (P-FF) has been considered as a popular alternative to the conventional master –slave based FF in the applications of high speed. First, a simple two-transistor AND gate design is used to reduce the ci...