This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft error on the internal nodes, and transmission gate and Schmitt-trigger circuit to filter out transient resulting from particle hit on combinational logic. The proposed circuit has low power consumption with negative se...

In this paper we present a current-mode VLSI implementation of shunting inhibition. Our approach uses translinear circuit design techniques using MOS transistors operating in the subthreshold region. Compared to previous implementations our design achieves a larger dynamic range and also clearly demonstrates the dependence of the spatio-temporal response of the network on the input light mean-i...

In this paper, an efficient bottom-up extraction approach is proposed to build accurate behavioral model for the switched-capacitor (SC) delta-sigma ( ) modulator. In the special extraction mode, we can use several specific patterns to obtain the key circuit parameters of the design in a short time without separating it into several sub-blocks. Actual loading effects and parasites can be consid...

A novel VLSI pipeline architecture for high-speed clockless computation is proposed. It features gate-level pipelining to maximize throughput and uses dynamic latches to keep the latency low. The most salient property is the asynchronous operation using a modi ed handshake protocol. Data words are accompanied by associated control signals resembling a local clock and propagate in coherent waves...

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit has been analyzed to fix the systemlevel ESD issues. The circuit performance to detect different positive and negative fast electrical transients ha...

A new biquadratic filter with three voltage-inputs and one voltageoutput and one current-output is presented. The filter employs two types of current conveyors, grounded resistors and grounded capacitors to realize the lowpass, highpass and bandpass responses by selecting different input signals. The proposed circuit has high input impedance, independent adjustments of angular frequency 0 and q...

This paper presents a new circuit arrangement for a current-mode Wheatstone bridge that is suitable for low-voltage integrated circuits implementation. Compared to the other proposed circuits, this circuit features severe reduction of the elements number, low supply voltage (1V) and low power consumption (<350uW). In addition, the circuit has favorable nonlinearity error (<0.35%), operate with ...

This article explains a new implementation of efficient D-Flip-Flop (DFF) using Gate-Diffusion-Input (GDI) technique, PowerPC, DSTC, and HLFF. This DFF design allows reducing power-delay product and area of the circuit, while maintaining low complexity of logic design. Performance comparison with other DFF design techniques is presented, with respect to gate area, number of devices, delay and p...

In this paper we studied accurate static power consumption in five well-known templates used in implementation of asynchronous circuits. The studied templates comprising PCHB, PCFB, STFB, HC and MOUSTRAP have been used to model a 5-stage 2-bit pipeline by HSPICE in 0.18um CMOS technology. In order to analyze the static power consumption, several behavioral studies were conducted and the results...

In this paper, we develop a set of delay estimation models with consideration of various interconnect optimization techniques, including optimal wire-sizing (OWS), simultaneous driver and wire sizing (SDWS), and simultaneous buuer insertion/sizing and wire sizing (BISWS). These models have been tested on a wide range of parameters and shown to have about 90% accuracy on average compared with ru...