The paper proposes architectures of 5:3 compressor designs for low power multiplication purposes. The architecture explores the essence of two transistor multiplexer design and novel two transistor XOR gates for the proposed topology with least number of transistors for logic level implementation. The modified and proposed compressor designs reduce the stage delays, transistor count, PDP (power...

In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing as to guarantee synchronously arriving signal slopes at the input of logic gates, thereby avoiding glitches. Since the delay of logic gates depends directly on transistor sizes, their variation allows to equalize different path delays without influencing the total delay of the circuit. Unfortuna...

In VLSI, scaling methods plays an important role in reducing the power dissipation from one technology node to other technology node. The two major constraints for delay in any VLSI circuits are latency and throughput. The negative bias temperature instability (NBTI) effect occurs when a pMOS transistor is under negative bias (Vgs= -VDD) increasing the threshold voltage of pMOS transistor and r...

This paper compares two different logic styles based on 45 nm technology for implementing logic gates of upto two inputs in terms of their layout area, delay and power dissipation. The XOR gate has been implemented & designed using CMOS & Pass Transistor logic on 45 nm technology .The schematic of proposed gate has been designed & simulated by using DSCH3& its equivalent layout has been develop...

A soft switching three-transistor push-pull(TTPP)converter is proposed in this paper. The 3rd transistor is inserted in the primary side of a traditional push-pull converter. Two primitive transistors can achieve zero-voltage-switching (ZVS) easily under a wide load range, the 3rd transistor can also realize zero-voltage-switching assisted by leakage inductance. The rated voltage of the 3rd tra...