We describe how a ladder emitter can implement tunable quantum logic gate on photonic qubits encoded in the frequency basis. The ground-to-first excited state of interacts with control photon, and first-to-second transition target photon. By controlling relative detuning between photon emitter, we enable any controlled-phase operation from 0 to π. derive analytical formulas for performance thro...

The field of AI is strewn with knowledge representation languages. The language designer typically has one particular application domain in mind: as subsequent types of applications are tried, what had originally been US&II j2urure.y become undesirable limitations, and the language is overhauled or scrapped. One remedy to this bleak cycle might be to construct a representational scheme whose do...

Starting from full quantum field theory, various mean field approaches are derived systematically. With a full consideration of external source dependence , the stationary phase approximation of an action gives a nuclear mean field theory which includes quantum correlation effects (such as particle-hole or ladder diagram) in a simpler way than the Brueckner-Hartree-Fock approach. Implementing f...

We present the ground state phase diagram of the two-leg Kondo ladder obtained through the density-matrix renormalization group. At half-filling, the spin and charge gaps are non-zero. At other conduction electron densities, we have found fully and partially saturated ferromagnetism, paramagnetism, and dimerized phases at special commensurate fillings. r 2005 Elsevier B.V. All rights reserved. ...

The Heisenberg model on a 2-chain spin-12 ladder with frustrating second neighbor interactions is studied by using series expansions about the Ising and dimer limits, numerical diagonalization, and by Abelian bosonization analysis. The phase diagram is determined, and pair correlations and the complete dispersion relations for the triplet spin-wave excitations are also computed. PACS Indices: 7...

Two architectures for a 1-V, 10-bit 200-kS/s successive approximation analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 μm digital process are presented. A track-andhold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch with a novel rail-to-rail trackand-latch comparator circuit is described. A pMOS-only ladder containing a rail-to-ra...

Proposed is a system that recognizes logic symbols and their inter{connections on logic diagrams. Input diagram, digitized by scanner, is converted into a set of line segments through a sequence of picture processing operations. Then symbols and connections are extracted by identifying loops and rectilinear polylines utilizing model{base in which symbols are graphically described. Experiment wi...