We consider a class of non-planar graphs that arises in VLSI layout compaction and show that a number of shortest path problems on these graphs can be solved in the same time as the corresponding problem in a planar graph.

Due to continuous technology scaling, the interconnect delay and power reduction is becoming one of the most important design challenges. In this paper, we present a novel algorithm for simultaneous multilayer interconnect spacing so that on the one hand the total power of interconnect is reduced and on the other hand, delay constraints are not violated. We first present an optimization problem...

Given a graph G with weighted edges, and a subset of nodes T , the T -join problem asks for a minimum weight edge set A such that a node u is incident to an odd number of edges of A i u 2 T . We describe the applications of the T -join problem in sparse graphs to the phase assignment problem in VLSI mask layout and to conformal re nement of nite element meshes. We suggest a practical algorithm ...

The problem of general block placement in VLSI is the topic of this paper. Among the existing approaches to its solution we concentrate on the constructive one, where blocks are selected and located one at a time. Two of the main features of the constructive approach are its high computational efficiency and its ability to support both automatic and interactive placement. We present some well-k...

We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer sizing and wire sizing problem. We propose a simple buffering architecture for this problem and show that this architecture achieves a near optimal solution. We also derive simple models for a buffered wire which are suit...

Let P be a set of n points in a metric space. A Steiner Minimal Tree (SMT) on P is a shortest network interconnecting P while a Minimum Spanning Tree (MST) is a shortest network interconnecting P with all edges between points of P . The Steiner ratio is the infimum over P of ratio of the length of SMT over that of MST. Steiner ratio problem is to determine the value of the ratio. In this paper ...

In this paper we address the L∞ Voronoi diagram of polygonal objects and present applications in VLSI layout and manufacturing. We show that in L∞ the Voronoi diagram of segments consists only of straight line segments and is thus much simpler to compute than its Euclidean counterpart. Moreover, it has a natural interpretation. In applications where Euclidean precision is not particularly impor...

The study of nontraditional notions of visibility and convexity is a fruitful branch of geometry, which has found applications in vlsi design, graphics, and motion planning. Researchers have investigated multiple variations of these notions, including orthogonal, finitely oriented, and restricted-orientation visibility and convexity, as well as nesw and link convexity. Rawlins introduced the no...

We consider a class of non-planar graphs that arises in VLSI layout compaction and show that a numuer of shortest path problems on these graphs can be solved in the same time as the corresponding problem in a planar graph.

We present dual heuristics for the directed cut formulation of the Steiner problem in graphs. These heuristics usually give tight lower and upper bounds, and are enough to quickly solve two thirds of the instances from the literature. For harder instances, we propose two exact algorithms using those heuristics: branch-and-ascent, an implicit enumeration without LP solving; and a branch-and-cut ...