In this work, we present a 200 MHz to 1.6 GHz digital delay-locked loop (DLL) for per-pin deskew applications. The proposed phase shifters apply linear and scalable circuit architecture for the pin-to-pin delay mismatch of parallel I/O pins. The proposed phase detector with a detection window and the proposed consecutive phase decision method reduce the sensitivity to reference clock jitter. A ...

Loop closing is a vital component for mobile robot navigation without a priori information of the environment, since the mobile robot has to explore, build and at the same time maintain a globally consistent map. Moreover, it allows the mobile robot to recover from positional drifts due to errors associated with sensor measurements once loop closing is performed. In this paper, an active loop c...

This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs). A reference loop generates quadrature clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to generate the output clock in a main loop. This architecture enables the DLL to emulate the infinite-l...

We demonstrate simultaneous demultiplexing, data regeneration and clock recovery at 10Gbits/s, using a single semiconductor optical amplifier-based nonlinear-optical loop mirror in a phase-locked loop configuration.

An injection-locked ring oscillator-based phase-locked-loop targeting clock recovery for space application at 3.2 GHz is presented here. Most circuits need a very low phase noise and jitter performance are thus based on LC-type oscillators. These excellent performances come the expense of poor integration density. To alleviate this issue, work introduces an PLL circuit. The combination injectio...

Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of ea...

This report summarizes a software de…ned phase locked loop and its connection to standard second-order loop design parameter for a integrating VCO and DDFS frequency synthesizer. 1 Introduction Phase locked loops (PLLs) have been used since the early development of radio. Critical paper collections [1] and books [2] cover the subject matter, which includes nonlinear feedback and stochastic di¤e...