Purpose – The purpose of the paper is to introduce the Dynamic Phasor Modelling (DPM) approach for stability investigation and control design of single-phase Phase Locked Loops PLLs. The aim is to identify the system instabilities not predicted using the existent analysis and design methods based on the simplified average model approach. Design/methodology/approach – This paper starts by invest...

An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. ...

Novel frequency doubler circuits and dividers for clock signal generation are presented. In combination with two edge detectors and two duty cycle control buffers a low cost frequency doubler circuit is achieved as compared to Phase-Locked Loop (PLL) design. An input clock signal with an unpredictable duty cycle is inputted to a rising (or falling) edge detector. The edge detector converts the ...

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm ...

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circ...

A novel Phase-Locked Loop scheme is proposed in this paper, whose main distinguishing features are infinite hold-in range, pull-out range fractionally constant and also a ripple fractionally constant. To this end, it incorporates a variable gain amplifer and a frequency tunable loop filter. The driving application is the on-chip automatic tuning of slave filters, although the PLL architecture c...

PLL Basics A phase-locked loop is a feedback system combining a voltagecontrolled oscillator and a phase comparator so connected that the oscillator frequency (or phase) accurately tracks that of an applied frequencyor phase-modulated signal. Phase-locked loops can be used, for example, to generate stable output frequency signals from a fixed low-frequency signal. The first phase-locked loops w...

The All-Digital Phase-Locked Loop has several advantages when compared with traditional charge-pump based PLL. We will introduce some of its advantages in this paper, showing how they can be used to improve the system’s performance. In addition, performance limitations of the system will be discussed.

Synchronization is the key part to ensure high performance of grid-connected systems. Phase-locked loop (PLL) one most popular synchronizations due its simple implementation and robustness under certain grid variations. Particularly, in single-phase applications, PLL based on second-order generalized integrator (SOGI-PLL) widely used because structure, filtering ability frequency adaptability. ...

Frequency-modulated continuous-wave (FMCW) radars necessitate fast frequency modulation. However, finite loop bandwidth of a phase-locked (PLL) limits the accuracy This paper proposes phase compensation (PC) technique to address this limitation. The synthesizer PLL with PC realizes and precise triangular chirp modulation by adding compensating square wave before integral path filter. is designe...