We evaluated the performance of three CMOS current-mode, multivalued adder circuits in terms of area (reduced interconnect), speed, and power consumption and compared them to their binary, voltagemode counterparts. We present the simulation results of these circuits, and one new circuit which has fewer transistors than any voltage-mode full adder. Our results, however, show that while current-m...

Parallel Prefix Adders have been established as the most efficient circuits for binary addition. The binary adder is the critical element in most digital circuit designs including digital signal processors and microprocessor data path units. The final carry is generated ahead to the generation of the sum which leads extensive research focused on reduction in circuit complexity and power consump...

This study proposes a new high performance and low power adder using new design style called probabilistic is proposed. The design of a probabilistic adder that achieves low power and high speed operation. The delay and power dissipation are reduced by dividing the adder into two parts to reduce the carry chain. This dividing approach reduces active power by minimizing extraneous glitches and t...

Quantum-dot cellular automata (QCA) is a newly-developed nanotechnology for next-generation nanoelectronic circuits. QCA circuits use the propagation of charge polarity in QCA cells to pass information without any current being involved. It has the advantages of extremely small size, low power consumption, high device density and twinkling operation process. Nanofabrication of QCA circuits may ...

This paper describes the comparison of VLSI architectures on the basis of Speed, Area and Power of different type of Adders like Carry Chain Adder, Carry Look Ahead Adder, Carry Skip Adder, and Carry Select Adder and 32-bit pipelined Booth Wallace MAC Unit with Carry Chain Adder, Carry Look Ahead Adder, Carry Skip Adder, and Carry Select Adder is designed in which the multiplication is done usi...

Abstract This paper presents two adder compressors architectures addressing high-speed and low power. Adder compressors are used to implement arithmetic circuits such as multipliers and digital signal processing units like the Fast Fourier Transform (FTT). To address the objective of high-speed and low power, it is well known that optimization efforts should be applied in all abstraction levels...

Design of high speed and low power data path logic systems are one of the most challenging areas of research in VLSI system design. Adder circuit is the main building block in DSP processor. However, Digital adders suffer with the problem of carry propagation delay. To alleviate this problem Carry Select Adder (CSLA) are used in computational unit. Carry Select Adder one of the fastest adder am...

A standard cell based gate level synchronous full adder design is presented in this paper. The main highlight of the article is that the proposed full adder realization is found to be better in terms of power-delay product (PDP), even in comparison with the full adder element that has been made available as part of two commercial standard cell libraries viz. the high-speed 130nm Faraday (UMC) b...

Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI digital signal processing (DSP) systems. One of the most widely used operations in DSP is finite-impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a progra...

A circuit design for a new high speed and Low Power 4-bit Braun Multiplier is presented. The multiplier is implemented by using different power reduction techniques. To design a multiplier it is necessary to design an AND gate and Full Adder circuit using the power reduction techniques is presented. The design uses CMOS digital circuits in order to reduce the power dissipation while maintaining...