scaling challenges and limitations of conventional silicon transistors have led the designers to apply novel nano-technologies. one of the most promising and possible nano-technologies is cnt (carbon nanotube) based transistors. cnfet have emerged as the more practicable and promising alternative device compared to the other nanotechnologies.  this technology has higher efficiency compared to t...

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1uA input bias current at 0.8 um technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. W...

A low latency, low power LDPC decoder design is presented in the paper. Partial-parallel check node processors are designed to reduce the decoding latency with moderate complexity; the parity check matrices of the LDPC codes are column-wise reordered to facilitate the parallel processing. Meanwhile, an efficient early stopping algorithm is proposed to stop the ‘undecodable’ words so that at lea...

Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP design...

In this paper, 1 bit full adder is built under a new hybrid logic (combination of PTL and CMOS logic) style, using 14 MOSFETs. Here we use 6transistor XOR-XNOR circuit to implement the full adder. This full adder offers full voltage swing at every nodes, higher density and high speed than the conventional CMOS design style. TSPICE is the simulator used for the simulation and bsim3v32 technology...

A low-voltage and low-power voltage mode adder/subtractor using MOSFETs in weakinversion is presented in this paper. Since the MOSFETs in the proposed circuit are biased in weak inversion, consequently its power dissipation is very low. The proposed circuit has been simulated with the HSPICE using a N-well 0.35μm 2p4m process and the results show that, under the supply voltage of 1V, the power ...

These course notes provide an introduction to topics in the design of Low-Voltage Low-Power (LV-LP) Analog CMOS design. The course is suitable for professional designers of analog circuits and graduate engineers wishing to acquire knowledge in this area.

This paper presents the application of reinforcement learning in automatic analog IC design. In this work, the Multi-Objective approach by Learning Automata is evaluated for accommodating required functionalities and performance specifications considering optimal minimizing of MOSFETs area and power consumption for two famous CMOS op-amps. The results show the ability of the proposed method to ...

a complete procedure for the design of w-band low noise amplifier in mmic technology is presented. the design is based on a simultaneously power and noise matched technique. for implementing the method, scalable bilateral transistor model parameters should be first extracted. the model is also used for transmission line utilized in the amplifier circuit. in the presented method, input/output ma...

This paper describes the system design of a lowpower wireless camera. A system level approach is used to reduce energy dissipation and maximize battery lifetime. System properties such as the network configuration and data statistics are exploited to minimize computational switching. Embedded power supplies systems are also used to minimize energy dissipation under varying temperature, process ...