The cascode NMOS architecture has been tested by the Human Body Model (HBM), Machine Model (MM) and Transmission Line Pulse Generator (TLP) in this paper. For the TLP, detailed silicon data have been analyzed well in many parameters, such as the first triggeringon voltage (Vt1), the first triggering-on current (It1), the holding voltage (Vh), and the TLP I-V curve. Besides the above three kinds...

Low power register file design plays an important role in an embedded processor. In this paper, we exploit register-usage in a program to find out unused registers, and turn these unused registers into low power mode by annotating power-controlling instructions. The whole work is performed by applying the hardware/software co-design principle. For the hardware part, we propose a voltage-scaling...