Morphine’s effects on learning and memory processes are well known to depend on synaptic plasticity in the hippocampus. Whereas the role of the hippocampus in morphine-induced amnesia and state-dependent learning is established, the biochemical and molecular mechanisms underlying these processes are poorly understood. The present study intended to investigate whether administration of morphine ...

Hierarchical block matching is an eecient motion estimation technique which provides an adaptation of the block size and the search area to the properties of the image. In this work, we propose two novel special-purpose architectures to implement hierarchical block matching for real-time applications. The rst architecture is memory-eecient, but requires a large external memory bandwidth and a l...

Modern architecture research relies heavily on detailed pipeline simulation. Simulating the full execution of an industry standard benchmark can take weeks to months. Statistical sampling and techniques like SimPoint that pick small sets of execution samples have been shown to provide accurate results while significantly reducing simulation time. The inefficiencies in sampling are (a) needing t...

For a human, episodic memory is a memory of past experiences that one gains over a lifetime. While episodic memory appears critical to human function, researchers have done little to explore the potential benefits for an artificially intelligent agent. In this research, we have added a task-independent, episodic memory to a cognitive architecture. To frame the research, we propose that episodic...

In this paper, we present a memory efficient VLSI architecture for 2-D Discrete Wavelet Transform (DWT) using lifting scheme. The advantages of lifting scheme are lower computational complexity, transforming signal without extension and reduced memory requirement. It decomposes the wavelet transform with finite taps into two coefficient sets named predictor and updater. Base on the lifting sche...

In this paper, a novel stock trading framework based on a neuro-fuzzy associative memory (FAM) architecture is proposed. The architecture incorporates the approximate analogical reasoning schema (AARS) to resolve the problem of discontinuous (staircase) response and inefficient memory utilization with uniform quantization in the associative memory structure. The resultant structure is conceptua...

Memory partitioning is an e ective approach to memory energy optimization in embedded systems. Spatial locality of the memory address pro le is the key property that partitioning exploits to determine an eÆcient multi-bank memory architecture. This paper presents an approach, called address clustering, for increasing the locality of a given memory access pro le, and thus improving the eÆciency ...

DASH is a scalable shared memory multiprocessor architecture which employs directory based cache coherence. Due to the physical distribution of the memory in DASH, there is potential for long memory latency. Although a number of latency reducing and hiding techniques such caching, a weaker memory consistency model, and pre-fetching are employed by DASH, the use of Multithreaded processors is no...