An unsigned 8-bit ÷ 4-bit delay-insensitive iterative divider is developed using the NULL Convention Logic paradigm. The divider is simulated using a 0.5μm CMOS process with static cells. The simulation of the initial design yielded an average cycle time of 75.92 ns with a transistor count of 4,721. A subsequent design increased throughput by 18%, while only increasing area by 2.7%.

The traceability chain to derive the capacitance unit from the quantum Hall resistance coaxial bridges. These bridges employ a inductive voltage divider to provide the voltage ratio needed. One such divider has recently been constructed calibrated at Inmetro. The design techniques responsible for the small ratio errors of the device are detailed

We realize and investigate a wavelength-flexible phase-coherent all-optical frequency-by-2 divider. Frequency division is obtained via self-phase locking in a degenerate continuous-wave (cw) optical parametric oscillator (OPO). The wavelength flexibility of the divider is based on the use of quasiphase matching (QPM) with perpendicular polarizations of the OPO output waves (type II). Mutual inj...

An 8-bit programmable square finder cum frequency divider architecture is presented. This special architecture includes a high speed parallel counter, clock trigger circuit, eight bit multiplier logic, sequence termination logic and sequence restarter logic. The entire architecture is divided into two parts: The frequency divider section and the square finder section. The frequency divider circ...

The Karlsruhe Tritium Neutrino Experiment (KATRIN) aims to determine the absolute mass of the electron antineutrino from a precise measurement of the tritium β-spectrum near its endpoint at 18.6 keV with a sensitivity of 0.2 eV/c. KATRIN uses an electrostatic retardation spectrometer of MAC-E filter type for which it is crucial to monitor high voltages of up to 35 kV with a precision and long-t...

This letter presents a new triple-band four-way filtering power divider (FPD) with greatly improved frequency selectivity and in-band isolation. By elaborately developing multi-port multi-mode topology between four identical resonators feedlines, FPD is attained. In order to validate the feasibility of proposal, one prototype designed, fabricated, measured. Both simulated measured results desig...

The purpose of my project is to design & simulate the frequency divider using ADS software. My project is totally emphasized on the IEEE 802.11 a standard. The IEEE 802.11a describes the WLAN standard. The basis of the project is the SCL (Source Coupled Logic). This thesis organization provides an overview of the evolution of digitally programmable FREQUENCY DIVIDER using CMOS technology.

A low-voltage and low-power current mode analog multiplier/divider design is presented in this paper. The based on operational transconductance amplifier (OTA) utilizing dynamic threshold MOS (DTMOS) structure consists of only three OTAs. circuit has the ability consuming low power requiring voltage supplies. 0.13µm IBM CMOS technology parameters are used to simulate suggested simulation result...

A compact fully integrated wideband six-port device composed of a suspended stripline Wilkinson power divider and three bias stripline of 3-dB quadrature directional couplers is presented. In order to integrate a six-port circuit, a multilayer circuit structure has been adopted by the via hole interconnection at the output port of the divider. The 3-dB quadrature directional coupler is composed...