The Multiplier Hopf Group Coalgebra was introduced by Hegazi in 2002 [7] as a generalization of Hope group caolgebra, introduced by Turaev in 2000 [5], in the non-unital case. We prove that the concepts introduced by A.Van Daele in constructing multiplier Hopf algebra [3] can be adapted to serve again in our construction. A multiplier Hopf group coalgebra is a family of algebras A = {A α } α∈π ...

In this paper, we present flexible multiprecision multiplier that combined variable precision, parallel processing (PP), razor based dynamic voltage scaling (DVS), and dedicated MP operand scheduling to provide optimum performance for variety of operating conditions. All of the building blocks of proposed flexible multiplier can either work as independent small precision multiplier or parallel ...

In this paper, we propose an MSD (most significant digit) multiplier based on an MSB (most significant bit) multiplier over GF(2). The proposed multiplier is based on connecting D (digit size)-bit bit-operations in series. In each digit operation in our proposed multiplier, the “left shift and reduction operation” is serially performed for each of D bits. Because registers for storing intermedi...

in this paper we introduce continuous $g$-bessel multipliers in hilbert spaces and investigate some of their properties. we provide some conditions under which a continuous $g$-bessel multiplier is a compact operator. also, we show the continuous dependency of continuous $g$-bessel multipliers on their parameters.

In this paper, a low-complexity Programmable Cellular Automata (PCA) based versatile modular multiplier in GF(2) is presented. The proposed versatile multiplier increases flexibility in using the same multiplier in different security environments, and it reduces the user's cost. Moreover, the multiplier can be easily extended to high order of m for more security, and low-cost serial implementat...

A low latency digit serial multiplier for GF(2m) that can be pipelined to the bit-level is presented in this paper. Unlike existing structures, the new multiplier does not put any restriction on the type of generator polynomial used or the digit size. Furthermore, the latency of the new multiplier is significantly less than the latency of the existing bit-level pipelined digit-serial multiplier...

assess the ecological effects of economic activity on the water, earth and man in the iranian economy approach using input - output tablewater is a vital resource for each biological and economic phenomenon. water is considered as a production input. production is not possible without water in all economic sectors. also, the environment including air, soil, fauna and plants utilize water in the...

A hybrid radix-4/radix-8 architecture targeted for high bit, general purpose, digital multipliers is presented as a compromise between the high speed of a radix-4 multiplier architecture and the low power dissipation of a radix-8 multiplier architecture. In this hybrid radix4/radix-8 multiplier architecture, the performance bottleneck of a radix-8 multiplier, the generation of three times the m...

1 Associate Professor, Department of Electronics and Communication Engineering, Nalla Narasimha Reddy Group of Institutions, Hyderabad, Telangana, India. 2 Assistant Professor, Department of Electronics and Communication Engineering, Nalla Narasimha Reddy Group of Institutions, Hyderabad, Telangana, India ---------------------------------------------------------------------***------------------...

This paper presents the design redundant Binary multiplier for 32*32bit number multiplication. Modern computer system is a dedicated and very high speed unique multiplier. Therefore, this paper presents the design a Redundant Binary multiplier. The proposed system generates M, N and interconnected blocks. By extending bit of the operands and generating an additional product the proposed system ...