In hard real-time embedded systems, switching to multicores is a step that most application domains delay as much possible. This mainly due the number of sources indeterminism, which involve shared hardware resources, such buses, caches, and memories. this paper, new task model considers interference execution causes in other tasks running on cores memory contention proposed. We propose schedul...

There has been a growing interest in recent years in mixed-criticality real-time systems in which tasks are attributed different levels of criticality based on the degree to which their deadlines must be assured. While most of the initial efforts on mixed-criticality systems targeted single-processor systems, the research community has recently started to investigate multiprocessor mixed-critic...

In the multi-core and multiprocessor research community, considerable work has been done on real-time multiprocessor scheduling algorithms where it is assumed the tasks are independent. However in practice a typical real-time system includes tasks that share resources. On the other hand, synchronization in the multiprocessor context has not received enough attention. In this paper we propose an...

In a shared memory multiprocessor system, two or more processors may simultaneously request the use of a shared resource. Therefore, an arbitration circuit is essential to resolve the contention among the competing processors and allocate the resource to the appropriate requesting processor (according to an arbitration protocol). A number of arbiter desians for multiDrocessor systems have been ...

A memory design based on logical banks is analyzed for shared memory mul-tiprocessor systems. In this design, each physical bank is replaced by a logical bank consisting of a fast register and subbanks of slower memory. The subbanks are buuered by input and output queues which substantially reduce the eeective cycle time when the reference rate is below saturation. The principal contribution of...