This paper presents a method to decompose an op-amp into its functional blocks. The is able recognize blocks on high level of abstraction, such as loads or amplification stages, which have large set possible structural implementations. hierarchical library With increasing hierarchy levels, the representation becomes more variable while function emerges. We use order automatically compute decomp...

The PLCs (Programmable Logic Controller) have been widely used to implement the safety-critical system such as RPSs (Reactor Protection System) in Korean nuclear power plants. Recently, there have been attempted to implement the software in RPSs by FPGAs (Filed-Programmable Gate Array) [1][2], due to the increasing maintenance cost of PLCs and the higher performance of FPGAs. The FPGAs are typi...

In this paper, a new broadcast encryption scheme is presented based on threshold secret sharing and secure multiparty computation. This scheme is maintained to be dynamic in that a broadcaster can broadcast a message to any of the dynamic groups of users in the system and it is also fair in the sense that no cheater is able to gain an unfair advantage over other users. Another important feature...

Encryption is an important issue in information security which is usually provided using a reversible mathematical model. Digital image as a most frequently used digital product needs special encryption algorithms. This paper presents a new encryption algorithm high security for digital gray images using genetic algorithm and Lattice Map function. At the first the initial value of Logistic Map ...

We show how to implement a deniable encryption method from secret sharing. Unlike the related concept of honey encryption, which employs preprocessing step in symmetric re-shape distribution plaintext towards making real indistinguishable ciphertext for fake message, we can avoid both, computational intractability assumptions and data. This accomplishes deniability against an attacker that forc...

This paper presents an automated procedure for the technology mapping of timed circuits to practical gate libraries. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the speciication which is used throughout the design process to optimize the implementation. Our procedure begins with a timed speciication and a delay-annotated gate library descr...

Extended Simple Colored Petri Nets (ESCP-nets) are a new class of High-level Petri Nets conceived as a good trade-off between Petri Nets (P-nets) and Colored Petri Nets (CP-nets), to be used in plant simulation. ESCP-nets, while being much more convenient and compact than P-nets, are fairly simpler than CP-nets, thus being more easily implemented and more amenable to formal analysis. Furthermor...

Retiming is a widely investigated technique for performance optimization. In general, it performs extensive modifications on a circuit netlist, leaving it unclear, whether the achieved performance improvement will still be valid after placement has been performed. This paper presents an approach for integrating retiming into a timing-driven placement environment. The experimental results show t...

Delay fault testing has proven to be a significant part of modern manufacturing testing. It has also become a source of overtesting due to detection of functionally untestable faults by invalid transitions that would not occur during functional operation of the chip. There has been previous work in the field that identifies these faults allowing them to be removed from active fault lists from A...

The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI has been a hot issue in recent years. In VLSI circuit partitioning, the problem of obtaining a minimum cut is of prime importance. With current trends, partitioning with multiple objectives which includes power, delay...