My main research is on asynchronous and mixed-timing digital design. Asynchronous circuits have no centralized or global clock. Instead, they are distributed hardware systems where multiple components coordinate and synchronize at their own rate on communication channels. As chips grow increasing larger and faster, power and design-time requirements become more aggressive, and timing variabilit...

Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today’s NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in the network is reduced significantly, which translates to improved network performance or reduced network bandwidth requirements and power co...

Network-on-chip (NoC) is considered as a promising paradigm to overcome the communication bottleneck of future multicore systems. As a basic component in on-chip router, arbiter has a big impact on the performance of router. In this paper, we propose a novel dynamically adaptive arbiter which is based on the round robin mechanism. The proposed arbiter detects buffer status of input ports and ch...

The performance of network-on-chip (NOC) largely depends on the underlying routing techniques. A routing technique has two constituencies: output selection and input selection. This paper focuses on the improvement of input selection part. Two traditional input selections have been used in NOC, firstcome-first-served (FCFS) input selection and Round-Robin input selection. Also, recently a conte...

In order to improve the performance of current embedded systems, Network -on-Chip (NoC) offers many advantages, especially in terms of flexibility and low cost. Applications require more and more intensive computations, especially multimedia applications such as video encoding. Developing product and application using such an architecture offers many challenges and opportunities. Many tools wil...

As multiprocessors scale to unprecedented numbers of cores in order to sustain performance growth, it is vital that the gains in speed not come with increasingly high energy consumption. Recent advances in 3D Integration (3DI) CMOS technology have made possible hybrid photonic networks-on-chip (NoC), which have the potential to result in high performance while consuming much less power than an ...

The design of integrated circuits will change a lot in near future. Because of shorter time-to-market it is impossible to design all functional blocks from scratch. The system designers are moving into higher abstraction levels and usage of reusable IP (Intellectual Property) blocks is increasing. The communication between the IP blocks is of increasing importance and thus also be designed in a...

Current and future communications systems have to provide a large degree of flexibility e.g. to provide multi-service ability, seamless roaming, softinfrastructure upgrading, user-defined propriety, simultaneous multi-standard operation, and different quality of service. This paper presents a multi-processor platform for the application domain of channel decoding. Inherently parallel decoding t...

This paper addresses the Network-on-Chip (NoC) application mapping problem. This is an NP-hard problem that deals with the optimal topological placement of Intellectual Property cores onto the NoC tiles. Network-on-Chip application mapping Evolutionary Algorithms are developed, evaluated and optimized for minimizing the NoC communication energy. Two crossover and one mutation operators are prop...

This paper presents a novel and efficient mapping algorithm, called Citrine. It generates a set of mappings which have nearly minimum possible distance between related cores results in reduction of communication cost in Network-on-Chip (NoC), while improving other performance metrics. Comparison of the communication cost results makes it obvious that final solutions found by our proposed approa...