Pipelining is a widely used technique for implementing architectures which have inherent temporal parallelism when there is an operational requirement for high throughput. Many variations on the basic theme have been proposed, with varying degrees of success. The aims of this paper are twofold. The first is to present a critical review of conventional pipelined architectures, and put some well ...

Software pipelining is a compile-time scheduling technique that overlaps successive loop iterations to expose operation-level parallelism. An important problem with the development of eeective software pipelin-ing algorithms is how to handle loops with conditional branches. Conditional branches increase the complexity and decrease the eeectiveness of software pipelin-ing algorithms by introduci...

This paper presents a new concurrent multiple-threaded architectural model, called superthreading, for exploiting thread-level parallelism on a processor. This architectural model adopts a thread pipelining execution model that allows threads with data dependences and control dependences to be executed in parallel. The basic idea of thread pipelining is to compute and forward recurrence data an...

E cient resource usage is a key to achieve better performance in parallel database systems. Up to now, most research has focussed on balancing the load on several resources of the same type, i.e. balancing either CPU load or I/O load. In this paper, we present oating probe, a strategy for parallel evaluation of pipelining segments in a shared-everything environment that provides dynamic load ba...

Spatial computing architectures promise a major stride in performance and energy efficiency over the traditional load/store devices currently employed large scale systems. The adoption of high-level synthesis (HLS) from languages such as C++ OpenCL has greatly increased programmer productivity when designing for platforms. While this enabled wider audience to target spatial architectures, optim...

In the context of mapping high-level algorithms to hardware, we consider the basic problem of generating an efficient hardware implementation of a single threaded program, in particular, that of an inner loop. We describe a control-flow mechanism which provides dynamic loop-pipelining capability in hardware, so that multiple iterations of an arbitrary inner loop can be made simultaneously activ...