Modular arithmetic operations l ike inversion, multiplication and exponentiation are used in several cryptography applications. A special modulo set of forms {21,2,2+1}are preferred over the generic modulo due to the ease of hardware implementation of modulo arithmetic functions as well as systemlevel intermodulo operations, such as RNS-to-binary conversion and sign detections. Key sizes in the...

This work describes the design of a divder technique Low-power techniques are applied in the design of the unit, and energy-delay tradeoffs considered. The energy dissipation in the divider can be reduced by up to 70% with respect to a standard implementation not optimized for energy, without penalizing the latency. In this dividing technique we compare the radix-8 divider is compared with one ...

SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are limited to radix-2 and radix-4. Higher radix dividers are therefore formed by a combination of low-radix stages. In this paper, we present an analysis of the effects of radix-2 and radix-4 SRT divider ...

It is considered to be the most suitable solution for large scale elections to design an electronic voting scheme using blind signatures and anonymous channels. Based on this framework, Okamoto first proposed a receipt-free voting scheme [30] for large scale elections. However, in the following paper, Okamoto [31] proved that the scheme [30] was not receipt-free and presented two improved schem...

In digital signal processing, the Fast Fourier Transform (FFT) is a kind of high efficient method to calculate the discrete Fourier transform (DFT). It cuts the discrete signal sequence which the length is N for different radix sequences to operate using the way of handing back and partition. Currently, the radix-2 FFT algorithm is a popular approach to do the transform work. However, its compu...

ÐThis paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder accordi...

This paper presents a mixed-decimation multipath delay feedback (M 2 DF) approach for the radix-2 k fast Fourier transform. We employ the principle of folding transformation to derive the proposed architecture, which activates the idle period of arithmetic modules in multipath delay feedback (MDF) architectures by integrating the decimation-in-time operations into the decimation-in-frequency-op...

In this paper three Real Factor FFT algorithms are presented. Two of them are based on Radix-2 and one on Radix-4. The computational complexity of Radix-2 and Radix-4 is shown as order N ~ 2 2 1 Nlog 4 and N Nlog 4 ~ 2 8 1 respectively unlike their standard counterparts N Nlog 5 ~ 2 and N Nlog 4 ~ 2 4 1 . Moreover, the proposed algorithms also require fewer multiplications than their standard F...

Orthogonal frequency division multiplexing (OFDM) is a popular method for wireless transmission of data at high rate. To increase the speed of transmission, the input high rate data stream is divided into many small data streams which are then transmitted parallel in OFDM system. The key component of OFDM system is the FFT processor. FFT converts the input time domain signal into frequency doma...

Aiming low power dissipation during testing, in this paper we present a methodology for deriving a novel BIST scheme for Modified Booth Multipliers. Reduction of the power dissipation is achieved by: (a) introducing a suitable Test Pattern Generator (TPG) built of a 4-bit binary and a 4-bit Gray counter, (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reduc...