In this paper, a novel reduced instruction set computer (RISC)- communication processor (RCP) has been designed with 32-bit operations which access 64-bit format and implemented using field programmable gate array (FPGA). The design of the RISC is facilitated like basic signals sine, cosine, square, modulation schemes amplitude modulation, shift keying, analog, digital quadrature modulation. Ad...

By abstracting the details of the data representations and operations in a microprocessor, term-level verification can formally prove that a pipelined microprocessor faithfully implements its sequential, instruction-set architecture specification. Previous efforts in this area have focused on reduced instruction set computer (RISC) and very-large instruction word (VLIW) processors. This work re...

The manner in which the resources of a microprocessor are used affects its performance, power consumption and size. In this work we show how increasing the size of a processor’s instruction set, in turn, increases the amount of hardware needed to implement that processor. We also study how efficiently the hardware resources of four processor architectures are used by measuring the static instru...

It was open for more than eight years to obtain an algorithm for computing the convex hull of a set of n sorted points in sub-logarithmic time on a reconfigurable mesh of size p n pn. Our main contribution is to provide the first breakthrough: we propose an almost optimal algorithm running in O((log logn)2) time on a reconfigurable mesh of size p n pn. With slight modifications this algorithm c...

This paper investigates Y UV -to-RGB color space conversion on FPGA-augmented TriMedia-32 processor. First, we outline the extension of TriMedia-32 architecture consisting of FPGA-based Reconfigurable Functional Units (RFU) and associated generic instructions. Then we analyse a YUV-RGB (RFU–specific) instruction which can process four pixels per call, and propose a scheme to implement the YUV-R...

This paper investigates inverse quantization on FPGA-augmented TriMedia processor. First, we outline the extension of TriMedia architecture consisting of FPGAbased Reconfigurable Functional Units (RFU) and associated generic instructions. Then we analyse an IQ-4 (RFU– specific) instruction which can process four coefficients per call, and propose a scheme to implement the IQ-4 operation on the ...

There are many computer architecture classification methods based data word length and size of the secondary storage), performance, instruction set, component base and others. instruction sets of the computer system, CISC, RISC, Quantum rotations: a case study in static and dynamic machine-code. best RISC (Reduced. Instruction Set Computer) processor ever designed. based RISC processor was desc...

Recently researchers have shown interest in integrating Reconfigurable logic into conventional processors as a Reconfigurable Function Unit (RFU). A context-full RFU supports holding intermediate results inside itself, which eliminates some data movement overheads and has some other benefits. Most contemporary processors support out-of-order execution and speculation. When a context-full RFU is...