One of the challenging tasks in code generation for embedded systems is register allocation and assignment, wherein, one decides on the placement and lifetimes of variables in registers. When there are more live variables than registers, some variables need to be spilled to memory and restored later. In this paper we propose a policy that minimizes the number of spills – which is critical for p...

This paper presents a jfloorplanner for datapath with the capability of re-allocating data storage for minimizing the interconnect area and critical path delay without altering the number of Functional units and the schedule. The tool has combined two novel approaches: 1 A placement & Routing model to handle different architectural topologies (mux. and/ or bus based) suitable for FPGA's. 2 An e...

The most creative step in synthesizing data paths executing software descriptions is the hardware allocation process. New algorithms for the simultaneous costlresource constrained allocation of registers, arithmetic units, and interconnect in a data path have been developed. The entire allocation process can be formulated as a two-dimensional placement problem of microinstructions in space and ...

Arithmetic function modules which are available in many circuits can be utilized to generate test patterns and compact test responses. Recently, it was shown that an adder or an accumulator cannot be used as a bit serial test pattern generator due to the poor random properties of the generated sequences. Thus, accumulator-multiplier or adder-multiplier structures have been proposed. In this pap...

An advanced approach to design a fault coverage test pattern generator by utilizing linear feedback shift register called Bit Swap-LFSR. This could perform fault analysis and also minimize the power utilization at circuit level during tests, by generating three intermediate patterns between random patterns by decreasing the hardware components usage. The main purpose of having intermediate patt...

Multi-recipient encryption schemes have many advantages such as high efficiency, low network cost, and flexible object control. An asymmetric multi-recipient encryption scheme with indistinguishability under chosen-ciphertext attack is proposed. The encryption scheme uses an eighth order linear feedback shift register. The main features of this scheme are small size of ciphertext and the overal...

Scan and ring schemes of the pseudo-ring memory selftesting are investigated. Both schemes are based on emulation of the linear or nonlinear feedback shift register by memory itself. Peculiarities of the pseudo-ring schemes implementation for multi-port and embedded memories, and for register file are described. It is shown that only small additional logic is required and allows microcontroller...

Marsaglia (2003) has described a class of“xorshift”random number generators (RNGs) with periods 2 − 1 for n = 32, 64, etc. We show that the sequences generated by these RNGs are identical to the sequences generated by certain linear feedback shift register (LFSR) generators using “exclusive or” (xor) operations on n-bit words, with a recurrence defined by a primitive polynomial of degree n.

Abstact A new design approach is proposed for a fault coverage circuit. In this design a linear feedback shift register which is called as LT_LFSR (Low Transition Linear Feedback Shift Register) is used. Using LT_LFSR reduces the power consumption by reducing the number of transitions during test mode. Power reduction is done by implementing two new test pattern generation methods in LFSR. In b...