An Application Specific Instruction set Processor (ASIP) is an important component in designing embedded systems. One of the problems in designing an instruction set for such processors is determining the number of registers is needed in the processor that will optimize the computational time and the cost. The performance of a processor may fall short due to register spilling, which is caused b...

The first self-stabilizing algorithm [1] assumed the existence of a central daemon, that activates one processor at time to change state as a function of its own state and the state of a neighbor. Subsequent research has reconsidered this algorithm without the assumption of a central daemon, and under different forms of communication, such as the model of link registers. In all of these investi...

Although technology advancement can pack more and more physical registers in processors, the numbers of architectured registers defined by the instruction set architectures (ISAs) remain relatively small on most modern processors. Exposing more architectured registers to compilers and programmers can improve the effectiveness of compiler optimization and the quality of code. However, increasing...

OBJECTIVE To compare the quality of care provided by general practitioners participating in diabetes shared-care registers with that provided by GPs not using registers. DESIGN Cross-sectional comparison using Health Insurance Commission (HIC) data for patients attending the GPs. PARTICIPANTS AND SETTING 155 GPs using diabetes registers, 459 GPs not using registers, and their patients with ...

It is now widely believed that FlexRay communication protocol will become the de-facto standard for distributed safety-critical automotive systems. In this paper, the fault sensitivity of the FlexRay communication controller registers are investigated using transient single bit-flip fault injection. To do this, a FlexRay bus network, composed of four nodes, was modeled. A total of 135,600 trans...

This paper proposes and evaluates software techniques that increase register file utilization for simultaneous multithreading (SMT) processors. SMT processors require large register files to hold multiple thread contexts that can issue instructions, out of order, every cycle. By supporting better inter-thread sharing and management of physical registers, an SMT processor can reduce the number o...

Prospective population based-registers of amyotrophic lateral sclerosis (ALS) have operated in Europe for over two decades, and have provided important insights into our understanding of ALS. Here, we review the benefits that population registers have brought to the understanding of the incidence, prevalence, phenotype and genetics of ALS and outline the core operating principles that underlie ...

Intelligent presentation of data requires exibility of expression based on user needs and data content, both of which evolve. This exibility is not ooered by the current generation of database management systems. To address this problem systematically we are developing editing tools to quickly build intelligent, user-tailored presentation systems for databases. Our presentation systems are call...

This paper introduces a new interesting research question concerning tasks. The weak-test-and-set task has a uniform solution that requires only two Multi-Writer Multi-Reader (MWMR) registers. Recently it was shown that if we take the long-lived version and require a step complexity that is adaptive to interval contention then, like mutual exclusion, no solution with finitely many MWMR register...

In program algebra, different instruction sets for Boolean registers are conceivable. In previous work on instruction sequence size complexity, we chose instruction sets for Boolean registers that contain only a few of the possible instructions. In the current paper, we study instruction sequence size bounded functional completeness of instruction sets for Boolean registers. This work is among ...