Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of retrieving input logic from an output logic because of bijective mapping between input and output. In this manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new ...

This paper proposes a novel reversible logic gate, NFT. It is a parity preserving reversible logic gate, that is, the parity of the outputs matches that of the inputs. We demonstrate that the NFT gate can implement all Boolean functions. It renders a wide class of circuit faults readily detectable at the circuit’s outputs. The proposed parity preserving reversible gate, allows any fault that af...

In the investigation of minimal machinery in reversible computing, we proved that each nondegenerate 2-state 3-symbol reversible logic element is logically universal. So far, a 2-state 4-symbol element called “rotary element” was shown to be logically universal in the framework of reversible logic element with memory. The main result in this paper not only improves the previous result with resp...

We propose the theory of Cayley graphs as a framework to analyse gate counts and quantum costs resulting from reversible circuit synthesis. Several methods have been proposed in the reversible logic synthesis literature by considering different libraries whose gates are associated to the generating sets of certain Cayley graphs. In a Cayley graph, the distance between two vertices corresponds t...

This study is about the design and analysis of a reversible logic based multiplexer, that is realized using carbon nano tube transistor. Reversible logic realization of the digital circuits offers numerous advantages over conventional circuit design. Power analysis was performed using HSPICE simulation software and the results are obtained for the 2×1 and 4×1 multiplexer transient behavior. The...

Reversible circuits can lead to low-power CMOS implementations and are also of interest in optical and quantum computing. In this paper, we consider the synthesis of reversible logic assuming a generalized Toffoli gate. We make use of Rademacher-Walsh spectral techniques and in particular a spectral measure of function complexity used as a metric in guiding the search for a solution. The synthe...

Non-Trivial Reversible Identities (NTRIs) are reversible circuits that have equal inputs and outputs. NTRIs of arbitrary size cannot be detected, in general, using optimization algorithms in the literature. Existence of NTRIs in a circuit will cause a slow down by increasing the number of gates and the quantum cost. NTRIs might arise because of an integration of two or more optimal reversible c...

The problem of synthesis and optimization of reversible and quantum circuits have drawn the attention of researchers for more than one decade. With physical technologies for realizing the quantum bits (qubits) being announced, the problem of testing such circuits is also becoming important. There have been several works for identifying fault models for reversible circuits, and test generation a...

| An 8 x 8-b nRERL serial multiplier is implemented in a 0.6m n-well 3-metal CMOS process. nRERL (nMOS Reversible Energy Recovery Logic) is a new reversible adiabatic logic circuit, which can be operated at the leakage-current level for ultralow-energy applications. Measurement results showed that the nRERL serial multiplier consumed only 0.9 % of the energy dissipation of the static CMOS one a...

This paper presents a heuristic cost minimization approach to synthes­ izing linear reversible circuits. Two bidirectional linear reversible circuit syn­ thesis methods are introduced, the Alternating Elimination with Cost Minimiza­ tion method (AECM) and the Multiple CNOT Gate method (MCG). Al­ gorithms, example syntheses, and extensions to these methods are presented. An MCG variant which inc...