This paper presents a design methodology to study RF circuit performance degradations due to hot carrier and soft breakdown. The experimental facts of DC stress on the RF properties of MOSFETs are given. The equivalent circuit model is developed and verified by measurement data. RF circuit such as a low noise amplifier is evaluated using SPICE circuit simulation. Noise figure and s-parameter de...

Bandpass sampling architectures, also called subsampling architectures, exhibit several advantages over super-het architectures. First, the complexity of subsampling architectures is significantly lower since no Phased-Locked-Loop (PLL) is required. A direct consequence is that downconversion from RF to IF can be achieved with significant power savings as compared to the super-het architecture....

In this work, we present a fully differential transimpedance amplifier (TIA) with controllable transimpedance for use in RF overlay downstream communication systems. The transimpedance amplifier has been designed in a standard 180-nm CMOS technology and it is intended for 47 MHz to 870 MHz subcarrier multiplexed RF signals. It performs a 18 dBΩ transimpedance gain control range for extended opt...

A dual RF-receiver preceded by discrete-step attenuators is implemented in 65nm CMOS and operates from 0.3– 1.0 GHz. The noise of the receivers is reduced by cross-correlating the two receiver outputs in the digital baseband, allowing attenuation of the RF input signal to increase linearity. With this technique a displayed average noise level below -169 dBm/Hz is obtained with +25 dBm IIP3, giv...

In this paper, the importance and perspective for the digitally-assisted analog and RF circuits are discussed, especially related to wireless transceivers. Digital calibration techniques for compensating I/Q mismatch, IM2, and LO impairments in cellular, 2.4GHz WiFi, and 60GHz WiGig transceivers are introduced with detailed analysis and circuit implementations. Future technology directions such...

A 1.2V 5GHz low-cost voltage-controlled oscillator (VCO) with active common mode feedback has been implemented in a CMOS/RF 90nm technology for a robust I/Q generation using a frequency divider-by-2 (DIV2). As the input common mode of the DIV2 affects critically its performance, a calibration method to correct the output common mode of the VCO has been proposed and validated through post-layout...

A complete 1.9GHz receiver, with BAW resonatorreferenced input matching network, is designed as a wakeup receiver for wireless sensor networks. The 90nm CMOS chip includes RF amplifier, PGA, ADC, and reference generation, while consuming 65μW from a single 0.5V supply. The input RF bandwidth of the receiver is 7MHz, while the maximum data rate is 100kbps. When detecting a 31-bit sequence, the r...

This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic lo...

We discuss state of the art and new developments for the characterization of CMOS technologies. In the first chapter the most important issues of MOS transistor modeling will be shown. Topics like AC/DC modeling, noise modeling and temperature modeling for the MOS transistor will be explained. State of the art MOS transistor models like the BSIM3 and BSIM4 models as well as the newest surface p...