A dynamic and optimal shop floor design, modelling and implementation is key to achieving successful Fractal Manufacturing System (FrMS). To build adaptive and fault-tolerant fractal layout, attention is paid to issues of shop floor planning, function layout, determination of capacity level, cell composition planning and flow distances of products. A full fledged FrMS. layout is multi-functiona...

BACKGROUND Human factors engineering has allowed a systematic approach to the evaluation of adverse events in a multitude of high-stake industries. This study sought to develop an initial methodology for identifying and classifying flow disruptions in the cardiac operating room (OR). METHODS Two industrial engineers with expertise in human factors workflow disruptions observed 10 cardiac oper...

A high-performance ASIC has been developed to serve as the interface for the 10-ns bus in the new AlphaServer 8000 series server systems from Digital. The CMOS standard-cell alternative (CSALT) technology provides a timing-driven layout methodology together with a correct-by-construction approach for managing the complex device physics issues associated with state-of-the-art CMOS processes. The...

Printed circuit board layout inspection methods are mostly based on local geometric information, therefor they are well suited to the CNN paradigm. Here the detection of two layout errors is considered namely, the breaks in the wires and some kind of short circuits. The designed analogic algorithms to solve the problems above were tested on real life examples using an experimental system based ...

in this paper, a mixed-integer linearized programming (minlp) model is presented to design a group layout (gl) of a cellular manufacturing system (cms) in a dynamic environment with considering production planning (pp) decisions. this model incorporates with an extensive coverage of important manufacturing features used in the design of cmss. there are also some features that make the presented...

| The paper proposes a new layout-driven multi-level logic factorization methodology for regular arrays of two-input cells, that can nd practical applications in ne-grain FPGA design, standard cell, gate matrix layout and sub-micron technologies. A new factorization algorithm for AND/OR/EXOR logic with multi-valued literals is introduced, that has application to minimization of Logic Cell Array...

This paper presents a hierarchical genetic algorithm (GA) to solve the cell formation and layout decisions of cellular manufacturing. The intrinsic features of our proposed GA include using a hierarchical chromosome structure to encode concurrent cell design and layout decisions, developing a new selection scheme to dynamically considering two highly correlated fitness functions, and proposing ...

The multipliers are the key structure for designing high performance digital systems. Design considerations of multiplier include high speed, less power consumption, less PDP (power-delay product) and regularity of layout. These design parameters make it suitable for various compact low power VLSI implementations. This paper presents an application of the proposed XNOR-XOR cell for a 2x2 array ...

When an over-the-cell routing layer is available for standard cell layout, efficient utilization of that routing space over the cells can significantly reduce layout area. In this paper, we present three physical models to utilize the area over the cells for routing in standard cell designs. We also present efficient algorithms to choose and to route a planar subset of nets over the cells so th...