Normally the SISCI interface provides a Distributed Shared Memory (DSM) [PTM97] abstraction using the Scalable Coherent Interface (SCI). This paper describes and discusses the design and the concepts behind a library called VIA2SISCI that we have developed. The library maps the semantics of the Virtual Interface Architecture (VIA) to SISCI–semantics and establishes a middleware between SISCI an...

In this paper we study how the potential advantages of distributed shared memory (DSM) techniques can be applied to concurrent object-oriented languages. We assume a DSM scheme based on an entry consistency memory model and propose an object model that can incorporate that DSM scheme. The object model is characterized by the requirement of explicitly enclosing object invocations between acquire...

In this paper, we characterize the performance of parallel $le transfers using the Zebra Striped Network File System by means of distributed discreteevent simulation model which uses a variation of the conservative timestamping technique. The simulator is a powerful tool that can be adapted to model related systems such as multiprocessors and distributed shared memory. Preliminary simulation re...

A new protocol using vectors of global timestamps for mutual exclusion in systems with Distributed Shared Memory (DSM) is described and some of its properties proved.

Parallel computers come in two varieties: those with shared memory and those without. The former are hard to build; the latter are hard to program. In this paper we propose a hybrid form that combines the best properties of each.

This paper addresses irregular loops compilation on Distributed Memory Parallel Computers (DMPCs) that provide a Shared Virtual Memory. Runtime techniques are introduced to distribute irregular loops so that page movements are reduced. Experimental results for the KSR1 are presented.

Asynchronous transfer mode (ATM) switches based on shared buffering are known to have better performance and buffer utilization than input or output queued switches. Shared buffer switches do not suffer from head of line blocking which is a problem in simple input buffering. Shared buffer switches have previously been studied under uniform and unbalanced traffic patterns. However, due to the co...