As the device size continues to shrink and circuit complexity continues to grow, power has become the limiting factor in today’s microprocessor design. Since the power dissipation is a function of many variables with uncertainty, the most accurate representation of chip power or macro power is a statistical distribution subject to process and workload variation, instead of a single number for t...

Asynchronous design has been considered to avoid problems like high clock frequency generation and distribution, as well as high static power consumption in GaAs digital circuits. This paper discusses the real advantages of implementing such circuits with respect to feasibility, speed performance, power dissipation and ease of design migration from CMOS to GaAs while taking into account several...

In the CMOS circuit power dissipation is a major concern for VLSI functional units. With shrinking feature size, increased frequency and power dissipation on the data bus have become the most important factor compared to other parts of the functional units. One of the most important functional units in any processor is the Multiply-Accumulator unit (MAC). The current work focuses on the develop...

Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be signiicantly reduced by a technique known as truncated multiplication. With this technique, the least ...

In this field research paper explores the design and analysis of Static Random Access memories (SRAMs) that focuses on optimizing delay and power. CMOS SRAM cell consumes very less power and have less read and write time. Higher cell ratios will decrease the read and write time and improve stability. PMOS semiconductor unit with fewer dimensions reduces the ability consumption. During this pape...

Each electronic circuit on the printed circuit board (PCB) is designed to operate over a limited range of DC voltage, outside of which circuit operation or performance is not guaranteed. A generalized view of the static voltage and associated tolerance is shown in Figure 1. In order to achieve high speed and low power dissipation, recent microprocessor , DSP and FPGA chips require voltage level...

LNS is applicable for low-power design at logic level because it reduces the bit activity. A design parameter that is often neglected despite playing a key role in an LNS-based processor performance is the base of the logarithm b [4], [5], as demonstrated in Fig. 1. The choice of base has a substantial impact on the average bit activity. Figure 1 shows activity per bit position; i.e., the proba...

A power efficient gain adjustment technique is described to realize programmable gain current mirror. The dissipation power changes over the wide gain range of structure are almost negligible. This property is in fact very interesting from power management perspective, especially in analog designs. The simple structure and constant frequency bandwidth are other ever-interesting merits of propos...

In this paper, we present a novel six-transistor (6T) single-ended static random access memory (SE-SRAM) cell for ultralow-voltage applications. The proposed design has a strong 2.65X worst case read static noise margin (SNM) compared to a standard 6T SRAM. A strong write-ability of logic ‘one’ is achieved, which is problematic in an SE-SRAM cell with a 36% improvement compared to standard 6T S...

This paper introduces a two-port BiCMOS static mem-ory cell that combines ECL level word-line voltage swings andemitter-follower bit line coupling with a static CMOS latchto achieve access times comparable to those of high-speedbipolar SRAM's, while preserving the high density and lowpower of CMOS memory arrays. The memory can be ac-cessed for read and write independentl...