The ADC architecture and timing diagram are shown in Figure 1. The converter consists of a 7b coarse flash stage, a 7b digital-to-analog converter (DAC), a subtractor. and a 6b fine flash stage. One-of-n decoders and ROhIs are used to convert the thermometer code outputs ofthe two flash stages to binarydata, that is thencorrecteddigitally to produce the final output. One bit ofredundancy. or ov...

We combine quantum dots (QDs) with long-lifetime terbium complexes (Tb), a near-IR Alexa Fluor dye (A647), and self-assembling peptides to demonstrate combinatorial and sequential bionanophotonic logic devices that function by time-gated Förster resonance energy transfer (FRET). Upon excitation, the Tb-QD-A647 FRET-complex produces time-dependent photoluminescent signatures from multi-FRET path...

This paper describes a framework and tools for automating the production of designs which can be partially recon gured at run time. The tools include: (i) a partial evaluator, which produces con guration les for a given design, where the number of con gurations can be minimised by a process known as compile-time sequencing; (ii) an incremental con guration calculator, which takes the output of ...

This paper presents a novel (low arithmetic unit count) hardware architecture for performing lifting-based JPEG2000's 513 Discrete Wavelet Transform (DWT). The architecture is built around parallel Shift-Accumulator Arithmetic Logic Units (ALUs) which can encode (with implicit embedded extension[S]) up to five levels of transformation. The proposed architecture, which consists of three adders, ...

A class of complementary IIR filters is introduced. One of these filters can be realized as a tapped cascaded interconnection of identical allpass subfilters. The complementary filter is then obtained automatically by adding some extra allpass subfilters and a subtractor. The proposed filters are always allpass complementary and, under certain conditions, also magnitude complementary. Further, ...

[email protected] 1 , [email protected] 2 , Abstract—the most timing critical part of logic design usually contains one or more arithmetic operations, in which addition is commonly involved. Addition is a fundamental arithmetic operation and it is the base for arithmetic operations such as multiplication and the basic adder cell can be modified to function as subtractor by adding ano...

Reversible logic enables ultra-low power circuit design and quantum computation. Quantum-dot Cellular Automata (QCA) is the most promising technology considered to implement reversible circuits, mainly due correspondence between features of QCA circuits. This work aims push forward state-of-the-art QCA-based circuits implementation by proposing a novel full adder\full subtractor (FA\FS). At fir...

A new 1-bit full adder (FA) cell illustrating low-power, high-speed, and a small area is presented by combination of transmission gate (TG), pass transistor logic (PTL), float techniques. Using the proposed cell, 4:2 compressor implemented its performance investigated under diverse circumstances voltage, temperature, driving. The process corners are evaluated through process-voltage-temperature...

application of quantum-dot is a promising technology for implementing digital systems at nano-scale.  quantum-dot cellular automata (qca) is a system with low power consumption and a potentially high density and regularity. also, qca supports the new devices with nanotechnology architecture. this technique works based on electron interactions inside quantum-dots leading to emergence of quantum ...