This paper describes a hybrid BIST methodology for testing systems-on-chip. In our hybrid BIST approach a test set is assembled, for each core, from pseudorandom test patterns that are generated on-line, and deterministic test patterns that are generated off-line and stored in the system. The deterministic test set is specially designed to shorten the pseudorandom test cycle and to target rando...

With the progress of deep submicron technology and increasing design complexity, hundreds of memory cores with different size and configuration are embedded in system-on-chips (SoCs). These memory cores occupy a noticeable silicon area and need an efficient and low-cost test methodology. Built-in Self-test (BIST) is a practical solution provides a certain degree of reliability and flexibility. ...

The purpose of this paper is to discuss how a recently proposed RT (Register Transfer) Level test preparation methodology can be reused to drive innovative LowEnergy (LE) / Low-Power (LP) BIST solutions for digital SOC (System on a Chip) embedded cores. RTL test generation is carried out through the definition of a reduced set of masks, forcing few "care" bits, and leading to a high correlation...

Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of large design space, which may result in a local optimum. In this paper, we present a method which aims to address the problem. Our method tries to find an optimal register assignment for each k-test session. Therefore, it offers a ran...

High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution. By proving the effectiveness ...

Built-In Self-Testing (BIST) of very large scale integrated circuits (VLSI) mainly consists of two components – test pattern generator (TPG) and output response analyze (ORA). Hence, under BIST, each of the inserted bypass storage cell (bscs) needs two flip-flops. This paper presents a novel architecture for ORA. The advantages of such architecture are that most bscs need one instead of two fli...

In this letter a histogram-based BIST (Built-In Self-Test) approach for deriving the main characteristic parameters of an ADC (Analog to Digital Converter) such as offset, gain and non-linearities is proposed. The BIST uses a ramp signal as an input signal and two counters as a response analyzer to calculate the derived static parameters. Experimental results show that the proposed method reduc...

We present a Built-In Self-Test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing con...

We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing con...

The hardware overhead and fault coverage of a circuit is an important problem in integrated circuits and systems. To overcome this problem pseudorandom built-in-self-test (BIST) generators have been widely utilized to test integrated circuits and systems. A Pseudorandom pattern generator (PRPG) is used for generating test patterns (TPG). A weighted Pseudorandom built-in-self-test (BIST) schemes...