Inspired by the developments in quantum computing, building domain-specific classical hardware to solve computationally hard problems has received increasing attention. Here, introducing systematic sparsification techniques, we demonstrate a massively parallel architecture: sparse Ising Machine (sIM). Exploiting sparsity, sIM achieves ideal parallelism: its key figure of merit - flips per secon...

Parallel machines are converging to a standard scalable architecture. A set of processors communicate through a network providing linear increases in bisection bandwidth, as the number of processors increase. Each processor also has a large local memory, providing linear increases in memory bandwidth. In addition, the support of uniform latencies removes the dependence of an algorithm on networ...

Running parallel database systems in an environment with heterogeneous resources has become increasingly common, due to cluster evolution and increasing interest in moving applications into public clouds. For database systems running in a heterogeneous cluster, the default uniform data partitioning strategy may overload some of the slow machines while at the same time it may under-utilize the m...

2014 In the first part of this paper, analogies between conventional rotating electromechanical machines (motors, alternators, etc...) and periodic-structure microwave electron tubes are made, and a common theory is elaborated. In the second part, this theory is used to define new types of rotating machines that will operate with electrical currents having a very wide frequency spectrum, or at ...

A parallel sorting algorithm is presented for storage-e cient internal sorting on MIMD machines. The algorithm rst sorts the elements within each node using a serial sorting algorithm, then uses a two-phase parallel merge. The algorithm is comparisonbased and requires additional storage of order the square root of the number of elements in each node. Performance of the algorithm on two general-...

{ Cache Coherent Non-Uniform Memory Access (CC-NUMA) architectures have received strong interests from both academia and industries. This paper studies the performance impact of design choices at diierent levels of address and memory mapping on CC-NUMA architectures. Through execution-driven simulations of ve numerical programs, we nd close interactions between data allocation, global address t...

We develop a framework on multi-head nite automata that allows us to study the relation of parallel logarithmic time and sequential logarithmic space in a uniform and nonuniform setting in more detail. In both settings it turns out that NC 1 requires data-independent computations|the movement of the input-heads only depends on the length of the input|whereas logarithmic space is caught with dat...

The class of weak parallel machines is interesting, because it contains some realistic parallel machine models, especially suitable for pipelined computations. We prove that a modification of the bulk synchronous parallel (BSP) machine model, called decomposable BSP (dBSP), belongs to the class of weak parallel machines if restricted properly. We will also correct some earlier results about pip...