Memory safety plays a crucial role in concurrent hardware/software systems and must be guaranteed under all circumstances. Although there exist some approaches for complete verification that can cope with both hardware and software and their interplay, none of them supports pointers or memory. To overcome this problem, we present a novel approach for model checking memory-related properties of ...

In this paper we present a model of a memory interface, which is a part of a radar system. The memory interface is modelled as a set of connected timed automata with UPPAAL extensions. The system is modeled and verified formally using the verification tool UPPAAL. The system safetiness, proper scheduling and the size of buffers are attempted to be verified and optimized. Partial-order reduction...

This work presents a Model Driven Engineering (MDE) approach for the automatic generation of a network of timed automata from the functional specification of an embedded application described using UML class and sequence diagrams. By means of transformations on the UML model of the embedded system, a MOF-based representation for the network of timed automata is automatically obtained, which can...

Bounded timed-arc Petri nets with read-arcs were recently proven equivalent to networks of timed automata, though the Petri net model cannot express urgent behaviour and the described mutual translations are rather inefficient. We propose an extension of timed-arc Petri nets with invariants to enforce urgency and with transport arcs to generalise the read-arcs. We also describe a novel translat...

Abstract When the simulation of a system, or verification its model, needs to be resumed in an online context, we face problem that particular starting state reached constructed, from which process is then continued. For timed automata, especially construction desired clock state, represented as difference bound matrix ( DBM ), can problematic, only limited set operations available, often does ...

As the complexity of designed Systems on Chip (SoC) increases, due to the ever growing number of transistors that can be integrated on a chip, methods have been developed to validate a design before it is actually manufactured. Currently, the method that is the most used is based on software simulation, which does not ensure that all the behaviors are correct. In order to provide exhaustive ver...

Timed automata are a very successful notation for specifying and verifying real-time systems, but timelocks can freely arise. These are counter-intuitive situations in which a specifier’s description of a component automaton can inadvertently prevent time from passing beyond a certain point, possibly making the entire system stop. In particular, a zeno-timelock represents a situation where infi...

In development of applications running on multi-processor system-on-chip (MPSoC) platforms, many interrelated choices have to be considered at the levels of the application, the operating system and the configuration of the platform. A major challenge is to develop correctly implemented systems together with good arguments for decisions taken. There are different frameworks for modelling and an...

The idea to use simulations (or refinements) as a compositional abstraction device is well-known, both in untimed and timed settings, and has already been studied theoretically and practically in many papers during the last three decades. Nevertheless, existing approaches do not handle two fundamental modeling concepts which, for instance, are frequently used in the popular Uppaal model checker...

This is a tutorial paper on the tool Uppaal. Its goal is to be a short introduction on the flavour of timed automata implemented in the tool, to present its interface, and to explain how to use the tool. The contribution of the paper is to provide reference examples and modelling patterns.