| Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-power (ULP) applications with low performance requirements. However, a large range of ULP applications continue to face performance constraints at certain times that exceed the capabilities of subthreshold operation. In this paper, we give two different examples to show that designing flexibility into ...

Abstract As a silicon-based microdisplay for Augment reality (AR), the high power dissipation of digital CMOS driver is significant barrier to approaching higher performance microdisplay. In this paper, new low-power SRAM cell with single bitline proposed reduce drivers. Compared conventional differential 6T cell, 9T uses single-ended read/write and separation technology by reducing adding word...

Wide attention has been focused on cryogenic CMOS (cryo-CMOS) operation because of its promising improvement devices’ and circuits’ performance wide application prospects. However, hot carrier degradation (HCD) limits the long-term reliability cryo-CMOS. This article investigates HCD in 0.18 μm bulk at temperature down to 4.2 K. Particularly, relationship between current overshoot phenomenon in...

A low-voltage compatible 120dB gain two-stage amplifier in standard digital CMOS with 3 transistors between VDD and VSS is presented and circuit details are discussed. With the use of precision voltage attenuator, output level monitoring circuits (OLMC) and a digital tuning network, the first stage was tested, achieving ≥76dB DC gains over 2Vpp output swing. With a modest-gain 2nd stage, ≥120dB...

A comprehensive study of the scaling negative capacitance FinFET (NC-FinFET) is conducted with TCAD. We show that NC-FinFET can be scaled to "2.1nm node" and almost "1.5nm comes two nodes after industry "3nm node," which has 16nm Lg last node according International Roadmap for Devices Systems (IRDS). In addition, intervening nodes, meet IRDS Ion Ioff target at target-beating VDD. The benefits ...

AIMS The efficacy and stability of the atrial electrode sensing function is essential for maintaining atrioventricular (AV) synchrony. This study aimed to explore the long-term reliability and causes of the long-term sensing failure of VDD systems. METHODS AND RESULTS We enrolled all the patients with complete or high-degree AV block who received VDD pacemakers between August 1994 to January ...

This paper compares areas between a 6T and 8T SRAM cells, in a dual-Vdd scheme and a dynamic voltage scaling (DVS) scheme. In the dual-Vdd scheme, we predict that the area of the 6T cell keep smaller than that of the 8T cell, over feature technology nodes all down to 32 nm. In contrast, in the DVS scheme, the 8T cell will becomes superior to the 6T cell after the 32-nm node, in terms of the are...

This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. We implemented a 256-Kb DW8T SRAM and a half-VDD generator with a 40-nm CMOS process. The measurement results of the se...