Fairness abstractions are useful for reasoning about computations of non-deterministic programs. This paper presents proof rules for reasoning about three fairness notions and one safety assumption with an automated theorem prover. These proof rules have been integrated into a mechanization of the Unity logic [13, 14] and are suitable for the mechanical verification of concurrent programs. Mech...

System quality is a key issue in modern systems development. Tool support is essential for checking the system quality efficiently. This is particularly true with respect to the dynamic interactions of the processes within a system. A first generation of checkers – model checkers – provide a basic technology for the verification of process-based systems. Conventional model checkers bear two dra...

We consider the problem of verification condition generation for Abadi and Leino’s program logic (AL) for objects. We provide an algorithm which to a given judgement J in AL computes a formula φ in first-order fixpoint logic such that φ is equivalent to the existence of a proof of J in AL. Moreover, we show that if J is sufficiently annotated, e.g., with loop invariants, then φ will be purely f...

In this paper we describe a method of automated test program generation intended for systematic functional verification of microprocessors. The method supplements such widely-spread practical approaches as software-based verification and random generation. In our method, construction of test programs is based on microprocessor model, which includes structural model and instruction set model. Th...

For specific domains (e.g., data analysis, planning and scheduling, or state estimation), automated program synthesis systems have been developed which are capable of producing hundreds of lines of non-trivial code. However, the potential applicability of an automatic program synthesis system does not only depend on size and quality of the generated code, but also its ability to be integrated i...

Embedded cores are being increasingly used in the design of large System-on-a-Chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrator. To reduce the verification complexity, the port order fault (POF) model proposed in [1] has been used for verifying core-based designs and the corresponding verification pattern generation have been develop...

We address the problem of verifying planning domains as used in model-based planning, for example in space missions. We propose a methodology for testing flight rules of planning domains which is selfcontained, in the sense that flight rules are verified using a planner and no external tools are required. We review and analyse coverage conditions for requirements-based testing, and we reason in...

Soundness of compositional reasoning rules depends on computational models and sometimes is rather involved. Since it is tedious to establish new rules, verifiers are forced to mould verification problems into a handful of proof rules available to them. In this paper, a syntactic approach to establishing soundness of proof rules in automated compositional reasoning is shown. Not only can our wo...

The MODUS project aims to provide a pragmatic and viable solution that will allow SMEs to substantially improve their positioning in the embedded-systems development market. The MODUS tool will provide a model verification and Hardware/Software co‐simulation tool (TRIAL) and a performance optimisation and customisable source‐code generation tool (TUNE). The concept is depicted in automated mode...