This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allows incorporation of both transient and permanent faults to varying levels of VHDL hierarchy, and helps in verifying the performance of a testable system.

This paper aims at surveying multipliers based on Horner’s rule for finite field arithmetic. We present a generic architecture based on five processing elements and introduce a classification of several algorithms based on our model. We provide the readers with a detailed description of each scheme which should allow them to write a VHDL description or a VHDL code generator.

These two benchmarks required the development of a virtual prototype and a hardware prototype, respectively, of a Synthetic Aperture Radar processor. The two RASSP Developers chose different approaches: one used COTS components on custom boards with a methodology emphasis on detailed VHDL prototyping and board design and one used COTS computer boards with a methodology emphasis on efficient VHD...

Methodical aspects are described to develop VHDL models of field bus systems. Field bus systems used in automatic control engineering are examples of distributed computing systems. Modelling of such a system is demonstrated with a Controller Area Network (CAN). The consideration ranges from the process to the control devices. Targets are functional verifications as well as performance predictio...

This paper describes STEVE, a syntax-directed editor for VHDL, which uses auto-completion and automatic template insertion to accelerate the entry of syntactically correct VHDL models. It is part of a larger project, VIDE, which integrates textual and graphical tools for HDL design entry. STEVE extends the SAVANT intermediate representation to deal with representation of templates and the onscr...

This report describes a method for and the results of an analysis of cholesterol and phospholipids in HDL2 and HDL3 and phospholipids in VHDL (d.>L 210) of patients with cerebral thrombosis, myocardial infarction and diabetes mellitus. After precipitation and elimination of LDL (low density lipoprotein) and VLDL (very low density lipoprotein) by Na phosphotangstate (NaPhT) and MgC12 and bringin...

This paper proposes a new testability analysis and test-point insertion method at the register transfer level (RTL), assuming a full scan and a pseudorandom built-in self-test design environment. The method is based on analyzing the RTL synchronous specification in synthesizable very high speed integrated circuit hardware descriptive language (VHDL). A VHDL intermediate form representation is f...

In this paper we present a family of Mixed-signal (mixed analog/digital) synthesis tools being developed at the University of Cincinnati. The VASE (VHDL-AMS Synthesis Environment) project involves the development of a vertically integrated synthesis environment centered around the emerging VHDL-AMS standard for specification of analog and mixed signal systems. The unique contributions of this r...

In this paper we present SAMSA, a new tool for the simulation of VHDL-AMS systems in Matlab. The goal is the definition of a VHDL framework in which analog/digital systems can be designed and simulated and new simulation techniques can be studied, exploiting both the powerful Matlab functions and Toolboxes.

In order to improve the precision and surface quality of Electrical Discharge Machining (EDM), the paper studies the application of complex programmable logic device (CPLD) used in pulse power for EDM, according to the characteristics of the device, using VHDL language input and schematic input method to design control circuit for EDM pulse power. Keyword: EDM; CPLD; VHDL language; pulse power