Aim of this paper is to propose a high-level power exploration framework based on an instruction-level energy model for VLIW (Very Long Instruction Word) architectures. More specifically, the present paper deals with the reduction of the complexity of the energy model of K -issue VLIW processors from exponential with respect to the number of operations within the Instruction Set O(|I S A|K ) to...

This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellent high-level language programmability, but require careful attention to VLSI and compiler design. Flexible, highbandwidth interconnect, high-connectivity register files, and fast cycle times are required to achieve rea...

Finite field arithmetic forms the mathematical basis for a variety of applications from the area of cryptography and coding. For finite fields of large extension degrees (as for cryptography), arithmetic operations are computation intensive and require dedicated hardware support under given timing constraints. We present a new architecture of a high performance VLIW processor that can perform b...

Much like VLIW, statically scheduled architectures that expose all control signals to the compiler offer much potential for highly parallel, energy-efficient performance. Bau is a novel compilation infrastructure that leverages the LLVM compilation tools and the MiniSAT solver to generate efficient code for one such exposed architecture. We first build a compiler construction library that allow...

We describe a new dynamic software scheduling technique for VLIW architectures, which compiles into VLIW code the program paths that are actually executed. Unlike trace processors, or DIF, the technique executes operations speculatively on multiple paths through the code, is resilient to branch mispredictions, and can achieve very large dynamic window sizes necessary for high ILP. Aggressive op...

A codesign approach for complex video compression systems is presented. The system is based on a exible and programmable VLIW (Very Long Instruction Word) architecture. The design approach can be subdivided into two phases: a quantitative analysis for deriving the main processor structure and a cosynthesis for generating the processor hardware and the compiler back-end. The analysis results of ...

EPIC processor is one of the best ways to exploit the instruction level parallelism where multiple instructions are issued explicitly by the compiler. VLIW processor is the evolution of EPIC processing paradigm. Very Long Instruction Word (VLIW) is multi-issue processors that try to extract parallelism statically by the compiler .It execute a long instruction that consist of multiple operation....

Due to their high computational demand, MPEG-2 video coding solutions have been based mainly on custom hardware (ASIC) systems. Such systems lack the flexibility and adaptability of software-based solutions. Achieving real-time MPEG-2 video encoding in software remains to be a major challenge. A typical MPEG-2 encoder performs 20 to 30 GOPS (Giga operations per second), which exceeds the capabi...

In this paper, we examine the trade-offs in performance and area due to customizing the datapath and instruction set architecture of a soft VLIW processor implemented in a high-density FPGA. In addition to describing our processor, we describe a number of microarchitectural optimizations we used to reduce the area of the datapath. We also describe the tools we developed to customize, generate, ...

The paper summarizes the FMT modulation prototype filter design and its efficient implementation on DSP. The optimum design of algorithms for digital signal processors with VLIW architecture is described. Using this new approach it was, for example, possible to optimize compilation from the C language into the assembler of TMS320C6414 digital signal processor for implementation of FMT modulatio...