This paper presents an architecture for the efficient and high-speed realization of morphological filters. Since morphological filtering can be described in terms of erosion and dilation, two basic building units performing these functions are required for the realization of any morphological filter. Dual architectures for erosion and dilation are proposed and their operations are described. Th...

A systematic graph-based methodology for designing optimal VLSI RNS (Residue Number System) converters from binary system to RNS to quadratic RNS (QRNS) and conversely, using full adders as the basic building block is introduced. The design methodology derives array architectures starting from the algorithm level and ending up with the bit level design. This methodology can be considered as a u...

This article presents simple and highly regular architectures for finite field multipliers using a redundant representation. The basic idea is to embed a finite field into a cyclotomic ring which has a basis with the elegant multiplicative structure of a cyclic group. One important feature of our architectures is that they provide area-time trade-offs which enable us to implement the multiplier...

The paper presents two new linear systolic architectures for the one-dimensional discrete Hartley transform (DHT). Both architectures exhibit several desired features such as regularity, modularity and high pipelineability, which make them amenable to VLSI hardware implementation. In addition these new architectures use the CORDIC (co-ordinate rotation digital computer) algorithm as the basic f...

Decoding in Residue Number System (RNS) based architectures can be a bottleneck. A high speed and flexible modulo decoder is an essential computational element to maintain the advantages of RNS. In this paper, a fast and flexible modulo decoder, based on the Chinese Remainder Theorem (CRT), is presented. I t decodes a set of residues into its equivalent representation in either unsigned magnitu...

In this paper, a new VLSI based Radix-4 FFT architecture is developed by combining the mixed radix and pipelining architectures. Proposed architecture named as “Radix-4 Combined Single Path Delay Feedback (SDF) Multipath Delay Commutator (MDC) FFT”. As the name itself, design of proposed FFT architecture is designed with the help of both SDF and MDC data flow structures. Both SDF and MDC archit...

VLSI Architectures for Modern Error-Correcting Codes CRC Press Book. Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary. An important class of multipleerror-correcting linear cyclic codes is the class of BCH codes. In fact, BCH code is a generalization of the cyclic Hamming codes. Error correction codes (ECCs) are deployed in digital communication systems to tion 4 recalls...

Integrated Systems Group is focused on several key design aspects of modern integrated systems. The group is focused on building cutting edge, energy-efficient integrated systems through vertical optimization encompassing communications and signal processing algorithms and architectures, and digital and mixed-signal circuits. The main research topics include modeling of noise and dynamics in ci...

This paper presents a fast algorithm along with its systolic array implementation for computing the 1-D Npoint discrete cosine transform (DCT), where N is a power of two. The architecture requires log,N multipliers and can evaluate one complete N-point DCT every N clock cycles. It possesses the features of regularity and modularity, and is thus well suited to VLSI implementation. As compared to...

Architecture and circuit design are the two most effective means of reducing power in CMOS VLSI. Mathematical manipulations, based on applying ideas from multirate signal processing have been applied to create high performance, low power architectures. To illustrate this approach, two case studies are presented – one concerns the design of a fast Fourier transforms(FFT) device, while the other ...