If uniform coding (Gödelization) of potentially infinite sequences of numbers can be performed in PSPACEF, then PSPACE = EXPTIME 6= EXPSPACE = 2-EXPTIME, and, for all p, we have p−EXPSPACE = p+1-EXPTIME; if it can be performed in LINSPACEF, we also have LINSPACE = DTIME(2); the proof fails, when relativized to oracle-TM’s. A by-product of this research is that PTIMEF is not closed under number-...

Hardware performance counters are available on most modern microprocessors. These counters are implemented as a small set of registers that count events related to the processor’s functions. The Perfctr toolkit is one of the most popular toolkits (for x86 processors) for monitoring these events. In this paper, it is used to discover the impact of L1 data cache misses on the overall performance ...

Return-Oriented Programming (ROP) is a sophisticated exploitation technique that is able to drive target applications to perform arbitrary unintended operations by constructing a gadget chain reusing existing small code sequences (gadgets). Existing defense mechanisms either only handle specific types of gadgets, require access to source code and/or a customized compiler, break the integrity of...

We motivate, define and design a simple static analysis to check that comparisons of floating point values use compatible bit widths and thus compatible precision ranges. Precision mismatches arise due to the difference in bit widths of processor internal floating point registers (typically 80 or 64 bits) and their corresponding widths when stored in memory (64 or 32 bits). The analysis guarant...

A system of simultaneously triggered clocks is designed to be stabilizing: if the clock values ever diier, the system is guaranteed to converge to a state where all clock values are identical, and are subsequently maintained to be identical. For an N-clock system, the design uses N registers of 2 log N bits each and guarantees convergence to identical values within N 2 \triggers".

Assumptions Intermediate language: RISC-like 3-address code‡ Intermediate Code Generation (ICG) is independent of target ISA Storage layout has been pre-determined Infinite number of registers + Frame Pointer (FP) Q. What values can live in registers? ‡ ILOC: Cooper and Torczon, Appendix A. Strategy 1. Simple bottom-up tree-walk on AST 2. Translation uses only local info: current AST node + chi...

Inherent within complex instruction set architectures such as x86 are inefficiencies that do not exist in a simpler ISAs. Modern x86 implementations decode instructions into one or more micro-operations in order to deal with the complexity of the ISA. Since these micro-operations are not visible to the compiler, the stream of micro-operations can contain redundancies even in statically optimize...

In this paper, we present an extension of active automata learning to register automata, an automaton model which is capable of expressing the influence of data on control flow. Register automata operate on an infinite data domain, whose values can be assigned to registers and compared for equality. Our active learning algorithm is unique in that it directly infers the effect of data values on ...

The impossibility of reaching deterministic consensus in an asynchronous and crash prone system was established for a weak variant of the problem, usually called weak consensus, where a set of processes need to decide on a common value in {0, 1}, so that both 0 and 1 are possible decision values. On the other hand, approaches to circumventing the impossibility focused on a stronger variant of t...

Abstrac t . Graph coloring is the dominant paradigm for global register allocation [8, 7, 4]. Coloring allocators use an interference graph, Z, to model conflicts that prevent two values from sharing a register. Nodes in 2: represent live ranges. An edge between two nodes indicates that they are simultaneously live azld, thus, cannot share a register. The allocator tries to construct a k-colori...