The elbow/no ocelli (elb/noc) complex of Drosophila melanogaster encodes two paralogs of the evolutionarily conserved NET family of zinc finger proteins. These transcriptional repressors share a conserved domain structure, including a single atypical C2H2 zinc finger. In flies, Elb and Noc are important for the development of legs, eyes and tracheae. Vertebrate NET proteins play an important ro...

NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a significant source of energy consumption and many attempts at energy efficient NoC synthesis have been proposed. However, in addition to the communication subsystem, the memory subsystem is an important contributor to chip ene...

A growing number of applications, often with real-time requirements, are integrated on the same system on chip (SoC), in the form of hardware and software intellectual property (IP). To facilitate real-time applications, networks on chip (NoC) guarantee bounds on latency and throughput. These bounds, however, only extend to the network interfaces (NI), between the IP and the NoC. To give perfor...

A true application-specific Network-on-Chip (NoC) requires the exact knowledge of the internal traffic behavior during the NoC is fully running the target application. Therefore, an accurate traffic measuring method is necessary. In this work, a simple but powerful traffic monitoring system is presented for the accurate evaluation and refinement of an application-specific NoC. The traffic monit...

In sub-65nm CMOS process technologies, networks-onchip (NoC) are increasingly susceptible to transient faults (i.e., soft errors). To achieve fault tolerance, Triple Modular Redundancy (TMR) and Hamming Error Correction Codes (HECC) are often employed by designers to protect buffers used in NoC components. However, these mechanisms to achieve fault resilience introduce power dissipation overhea...

Jin-Ho Ahn et al. 475 Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the p...