Testability, and design for testability, are widely discussed practical issues in software engineering, especially in protocol engineering. Existing definitions (or circumscriptions) of testability seem to be either quite vague, or, if more or less formal, then dedicated only to very special system models. Testability is usually decomposed into aspects like observability and controllability, an...

We propose a new design for testability technique, Parallel Serial Full Scan (PSFS), for reducing the test application time for full scan embedded cores. Test application time reduction is achieved by dividing the scan chain into multiple partitions and shifting in the same vector to each scan chain through a single scan in input. The experimental results for the ISCAS89 circuits showed that PS...

Attempts to commercialize GaN VCSELs have been unsuccessful to date due to the challenges of manufacturability of DBR mirrors, difficulties associated with current blocking, and the complexity of laser liftoff. The new process flow overcomes all three challenges enabling the manufacturing of IIINitride VCSEL without liftoff and with much reduced complexity and the possibility of on-wafer testing.

Purpose – The purpose of this paper is to report on podcasting experience by faculty and students in a South African higher education institution (HEI), identify issues, limitations and discuss implications for the design of future tools. Design/methodology/approach – This work consisted of two parts: semi-structured interviews with lecturers, content/curriculum developers and a student survey....

At-speed testing of high-speed circuits is becoming increasingly difficult with external testers. Therefore, empowering the chip to test itself seems like a natural solution. Hardware-based selftesting techniques have limitations due to performance and area overhead as well as problems caused by application of non-functional patterns. Another possible solution is software-based self-testing whe...

Present research in design for testability has largely been connned to the logic level. In this paper we present directions for research in design for testability at the layout or physical design level. These are illustrated for bridge faults in circuits consisting of CMOS standard cells.

The reliability of end-user developed spreadsheets is poor. Research studies find that 94% of ‘real-world’ spreadsheets contain errors. Although some research has been conducted in the area of spreadsheet testing, little is known about the behaviour or processes of individuals during the debugging task. In this paper, the authors investigate the performance and behaviour of expert and novice en...

Local Lorentz invariance is an important component of General Relativity. Testing for Local Lorentz invariance can not only probe the foundation stone of General Relativity but also help to explore the unified theory for General Relativity and quantum mechanics. In this paper, we search the Local Lorentz invariance violation associated with operators of mass dimension d = 6 in the pure-gravity ...

Attempts to commercialize GaN VCSELs have been unsuccessful to date due to the challenges of manufacturability of DBR mirrors, difficulties associated with current blocking, and the complexity of laser liftoff. The new process flow overcomes all three challenges enabling the manufacturing of IIINitride VCSEL without liftoff and with much reduced complexity and the possibility of on-wafer testing.

This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverage. The proposed approach works for any conventional full-scan design -no extra design-for-test (DFT) logic is required. If the peak power in a clock cycle during scan testing exceeds a specified limit (which depends on...