The principle of software radio architecture is investigated and applied for the implementation of a multi-standard terminal (MST) for operation with both current 2nd and future 3rd generation mobile radio systems. A key strategy for the design of the transceiver is to place the analog-to-digital converter (ADC) and digital-to-analog converter (DAC) as close as possible to the antenna. In addit...

A very low power mixed-signal design methodology based on subthreshold sourcecoupled circuits is presented, and a nano-Watt range analog-to-digital converter (ADC) circuit based on folding-interpolating topology is proposed as a complete design example. To reduce the power dissipation to sub-μW level, subthreshold source-coupled circuit family has been developed for both analog and digital part...

Narrowband radio transmitters like radio amateurs and broadcast radio stations are considered to be a serious problem for highbitrate data transmission over twisted pairs. Due to its high power level, radio frequency interference (RFI) has the potential of overloading the receiver’s analog-to-digital converter (ADC). Once the ADC is in saturation, any countermeasure taken in digital domain will...

This study aims to design analog-to-digital converter based on successive approximations (SAR ADC), with very low power consumption, in an advanced CMOS technology (28 nm), following the industrial methodologies IC. This project was conducted in partnership with Synopsys, operating at a supply voltage of 0.5 V ± 10% with a resolution of 12 bits and 500 kS/s sampling frequency. Keywords— Analog-...

A novel project is being presented here for implementation an auto ranging analog to digital converter for biomedical applications completely inside an FPGA i.e. an all-digital analog to digital (A/D) converter system. The only analog part is the auto ranging circuitry and an RC Integrator outside FPGA. The system outputs 24 bits and features a sigma delta ADC of 16 bits resolution, a range det...

The performance of Flash Analogto-Digital converter is greatly influenced by the choice of Comparator and Thermometer-toBinary encoder design. The work describes the design and pre-simulation of a , 3bit and an 4bit analog to digital converter for low power CMOS. It requires 2-1 comparators, an encoder to convert thermometer code to binary code. The design is simulated in cadence environment us...

This letter reports an extremely small differential non-linearity (DNL) in a cyclic analog-to-digital converter (ADC) using depletion-mode MOS (DMOS) capacitors for CMOS image sensors (CISs). Compared with conventional 1.5b digital-to-analog converter (DAC) configuration using 3 reference signals, the cyclic ADC with split sampling DMOS capacitors in the 1.5b DAC has the maximum DNL of +0.125/-...

Successive-approximation-register (SAR) analog-to-digital converters (ADCs) represent the majority of the ADC market for mediumto high-resolution ADCs. SAR ADCs provide up to 5Msps sampling rates with resolutions from 8 to 18 bits. The SAR architecture allows for high-performance, lowpower ADCs to be packaged in small form factors for today's demanding applications. This paper will explain how ...

This paper presents a 12-bit 2.32 GS/s time-interleaved pipelined/successive-approximation register (SAR) hybrid analog-to-digital converter (ADC) implemented in 28 nm CMOS. To achieve high-linearity at several GS/s, pseudo-differential push-pull input buffer with floating-body technique is proposed. A pipelined/SAR architecture dual-channel sampling multiplying digital-to-analog (MDAC) and one...

Implemented 5-bit 125-MS/s successive approximation register (SAR) analog to digital converter (ADC) on FPGA is presented in this paper.The design and modeling of a high performance SAR analog to digital converter are based on monotonic capacitor switching procedure algorithm .Spartan 3 FPGA is chosen for implementing SAR analog to digital converter algorithm. SAR VHDL program writes in Xilinx ...