Physical Unclonable Functions promise cheap, efficient, and secure identification and authentication of devices. In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in order to exploit the propagation delay differences of signals caused by manufacturing process variations. Multiple delay based PUF architectures have been proposed. However, we have observed inconsisten...

Performance of multipath transport protocols is known to be sensitive to path asymmetry. The potential difference between each path in terms of bandwidth, delay and packet-loss significantly decreases the overall performance when a single data flow is carried over multiple asymmetric paths. In this paper, we evaluate and analyse Concurrent Multipath Transfer extension of Stream Control Transpor...

OBJECTIVE Anthropometry (measurement of body dimensions) has been used for clinical diagnosis of growth and developmental disorders during pregnancy and after birth. Different brain volumes have also been shown in abnormal developmental disorders. This study compares the different horizontal diameters of the left- and right-hand thumbnails and asymmetry of lateral cerebral ventricles in childre...

Abstract Due to the rapid development in artificial intelligence, classic Von Neumann architecture is no longer able meet demands of high-computing, high-storage, and high-bandwidth intelligence applications. To address this issue, paper proposes a handwritten digit recognition accelerator based on systolic array. First, 5 convolutional layer network built. Besides, The FPGA-based convolution e...

the current study aims to review the cross sectional variation in cash flow asymmetric timeliness and its effect on conditional conservatism. in this study, data from 120 firms in tehran stock exchange for the period spanning 1384- 1390 were examined. the regression model used in this research is panel data method with fixed effects approach. the most common measure of conditional conservatism ...

In this paper, we study the performance of high-speed packet switches, where the switch fabric operates at a slightly higher speed than the links, i.e., a speeded-up switch. As link speeds keep increasing, the speedup of N (number of links) needed for pure output queueing (which is the best) becomes a significant technical challenge. This is one of the main reasons for the renewed interest in m...

We present several fast, practical linear-complexity scheduling algorithms that enable provision of various quality-of-service (QoS) guarantees in an input-queued switch with no speedup. Specii-cally, our algorithms provide per-virtual-circuit transmission rate and cell delay guarantees using a credit-based bandwidth reservation scheme. Our algorithms also provide approximate max-min-fair shari...