Asynchronous circuit elements are quiescent whenever they are not actually performing a computation, and thus they potentially waste less power than synchronous circuits. However, previous research on asymptotically non-dissipative computation has concentrated exclusively on synchronous computing models, while researchers on asynchronous circuits have ignored the issues of conservative, reversi...

This paper presents a new framework for asynchrony. This has its origins in our attempts to better harness the internal decision-making process of cellular automata (CA). Thus, we show that a max-plus algebraic model of asynchrony arises naturally from the CA requirement that a cell receive the state of each neighbor before updating. The significant result is the existence of a bijective mappin...

A testing scenario in the sense of De Nicola and Hennessy is developed to measure the worst-case eeciency of asynchronous systems using dense time, and it is shown that one can equivalently use discrete time. The resulting testing-preorder is characterized with some kind of refusal traces. Furthermore, the testing-preorder is reened to a precongruence for standard operators known from process a...

In this paper we present FASE (Fast Asynchronous Systems Evaluation), a tool for evaluating worst-case efficiency of asynchronous systems. This tool implements some well-established results in the setting of a timed CCS-like process algebra: PAFAS (a Process Algebra for Faster Asynchronous Systems). Moreover, we discuss some new solutions that are useful to improve the applicability of FASE to ...

This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which al...

Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an asynchronous interconnect. Such a scheme can be used for point-to-point communication in a globally asynchronous locally synchronous (GALS) system, a possible methodology for managing the predicted increase in clock do...

Formal verification is becoming a fundamental step in assuring the correctness of safety-critical systems. However, due to these systems being often asynchronous and even distributed, their behaviour can be very complex. Thus, their verification necessitates methods that can deal with huge or even infinite state spaces. In this paper we present how the integration of two advanced algorithms for...

Two digital systems working in different clock domains require a protocol to communicate with each other in order to ensure validity of the data being shared between the two systems. Such systems are said to be asynchronous, and the protocol used for communication is said to synchronize the two systems. Asynchronous design techniques are not as widely used as synchronous design techniques are. ...

The cycloaddition reaction of diphenylketene and cycloheptatriene is studied. The reaction proceeds via a highly asynchronous reaction path to the zwitterionic 6 as intermediate. Subsequent CC- bond formation yields 8, 8 diphenylbicyclo [4. 2. I] nona-2, 4-dien-7-one (1) and 7,7-diphenylbicycol [3.2.2] nona-2, 8-dien-ri-one (2) in a 1:1 ratio as formal [6+2] and [4+2] cycloaddition products

Theories defined in a process model are formalized and studied. A theory in a process calculus is a set of perpetually available processes with finite interactability, each can be regarded as a service, an agent behind the scene or an axiom. The operational and observational semantics of the theories are investigated. The power of the approach is demonstrated by interpreting the asynchronous π-...