Combinational equivalence checking is one of the key components in today’s hardware verification methodology. Structural similarity of the two designs are exploited by existing BDD, SAT, or ATPG based methods. This report presents a technique for improving the performance of the existing SAT-based combinational equivalence checkers by adding new constraints based on the structural similarity. O...

We introduce a formal mechanism for capturing test justification and propagation related behavior of blocks. Based on the identified test translation behavior, an RTL testability analysis methodology for hierarchical designs is derived. An algorithm for pinpointing the local-to-global test translation controllability and observability bottlenecks is presented. The analysis results are validated...

In this paper, we proposed a new ATPG (Automatic Test Pattern Generation) algorithm that can be easily implemented and learned by college level student while achieving fairly efficient fault coverage and fast generation time. Very high level algorithm and its decision tree have been illustrated. The output of the ATPG program is the set of test vectors generated by the new algorithm. The signif...

To create a combinational ATPG model for an acyclic sequential circuit, all unbalanced fanouts, i.e., fanouts reconverging with different sequential depths, are moved toward primary inputs using a retiming-like transformation. All flipflops are then shorted and unbalanced primary input fanouts are split as additional primary inputs. A combinational test vector for a fault in this model is conve...

Current paper describes a new environment MOSCITO for providing access to tools over the internet. The environment is built according to the master-slave concept, and it allows to encapsulate different EDA tools in order to form various work flows. In this paper we discuss integration of two systems for digital test into the MOSCITO environment. The first one is a hierarchical system DECIDER, w...

This paper presents an efficient parallel algebraic algorithm to implement ATPG for combinational circuits using the Boolean satisfiability on a distributed Computing environment. Path-Oriented Expanded Implication Graph(POE1G) of a combinational circuit is taken as a heuristics guide to improve the traditional stochastic calculation of Boolean satisfiability formula of a circuit. We propose a ...

Redundancy identification and removal is a critical step that typically follows logic synthesis or optimization. In principle, it should be possible to restrict the transformations applied by synthesis and optimization algorithms to those that preserve testability. In practice, however, few, if any, synthesis programs can guarantee the irredundancy of the logic circuits they produce. It may als...

Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost, testing using automatic test equipment (ATE) makes it hard to test the circuit while in the system. In this paper, we present a technique for built-in reseeding. Our technique requires no storage for the seeds. The s...

We present a new automatic test pattern generation algorithm for sequential circuits by traversing the partitioned state spaces. The new features include: (1) nondisjoint state groups are obtained such that two different state groups may have common flip-flops, (2) partial state transition graphs (STGs) are constructed at run time for each state group, (3) spectral information for state variabl...

The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates that the faults affecting the bit cells of the Look-Up Tables (LUTs) are not redundant, although they store constant values. We demonstrate that these faults cannot be neglected and that the fault model corresponding to ...