The VLSI layout designing is a highly complex process and hence a layout is often subjected to Layout Verification that includes (a) Design Rule Checking to check if the layout satisfies various design rules and (b) Connectivity Extraction to check if the components of the layout are properly electrically connected. In this work we study two geometric query problems which have applications in t...

Times are changing: After 14 years of working for the Macromolecular (and Advanced) journals, last seven which I have served as Editor-in-Chief family, am extremely happy and proud to hand over my official role esteemed colleagues. While success that family has had under leadership, these successes would not been possible without capable hands colleagues several years. It comes no surprise Dr. ...

The spline finite strip method (S.F.S.M.) for buckling analysis of plates and plate assemblies subjected to longitudinal compression and bending, transverse compression as well as shear is described. The method allows for the boundary conditions. Local buckling coefficients of plates with different boundary conditions under compression, bending and shear are calculated. Convergence studies with...

When creating an editor for a visual language, a challenging task is the layout specification. Many visual languages, e.g., Ecore diagrams or Petri nets, show similar layout characteristics, and hence reuse of layout behavior should be enabled. For that purpose, we introduce the concept of layout patterns, which encapsulates certain layout behavior. With the approach, it is possible to combine ...