Certain storage media such as flash memories use write-asymmetric, multi-level storage elements. In such media, data is stored in a multi-level memory cell the contents of which can only be increased, or reset. The reset operation is expensive and should be delayed as much as possible. Mathematically, we consider the problem of writing a binary sequence into writeasymmetric q-ary cells, while r...

This article studies the performance of unpaced serial production lines that are subject to breakdown and are imbalanced in terms of both of their processing time means (MTs) and buffer storage capacities (BCs). Simulation results show that the best pattern in terms of throughput is a balanced line With respect to average buffer level; the best configuration is a monotone decreasing MT order, t...

We introduce the N-buffer as a tool for multiresolution depth map representation. This neighborhood buffer encodes the value and position of local depth extrema at different scales in an image cube, in contrast to the image pyramid. The resulting increase in storage space is largely compensated by the following benefits: objects of any size can be culled in constant time against an occlusion ma...

A benchmark for the test of control scenarios of sequencing batch reactors (SBR) used for wastewater treatment is proposed. The plant layout includes a buffer tank for wastewater storage in front of the SBR. Performance criteria based mainly on the quality of the effluent are given. The use of the benchmark is illustrated by the study of the effects on the effluent of the control of dissolved o...

This paper very shortly describes some hardware solutions of central processor (CPU) of BESM-6. CPU had very deep instruction pipe with an associative buffer for instructions and an associative buffer for data with original protocol. Logical and storage elements used only domestic discrete components. Main logical unit based on differential amplifier with pyramid of rich diode logic and parapha...

Directly Executed Language (DEL) architectures are derived from idealized representations of high-level languages. DEL architectures show dramatic reduction in the number of instructions and memory references executed when compared to traditional architectures, offering the potential for designing highly cost-effective DEL processors. This report explains the design considerations for the data ...

This article studies the performance of unpaced serial production lines that are subject to breakdown and are imbalanced in terms of both of their processing time means (MTs) and buffer storage capacities (BCs). Simulation results show that the best pattern in terms of throughput is a balanced line With respect to average buffer level; the best configuration is a monotone decreasing MT order, t...

When a working set fits into memory, the overhead imposed by the buffer pool renders traditional databases noncompetitive with in-memory designs that sacrifice the benefits of a buffer pool. However, despite the large memory available with modern hardware, data skew, shifting workloads, and complex mixed workloads make it difficult to guarantee that a working set will fit in memory. Hence, some...

In this paper, we establish that maintaining a balanced workload on each machine over time stochastically minimizes the work-in-process inventory in certain types of flexible manufacturing systems (FM%) with finite or infinite common input buffer storage and an ample buffer et each machine. The results obtained here complement those obtained by Stecke and Morin (1985), in which it is establishe...

Crude wild pear lipoxygenase (LOX) from ripe Kurdistan wild pears was used in this study. Extracted crude LOX was assayed spectrophotometrically for raw, ripe wild pear lipoxygenase and after 7-day storage. The effects of different buffers and pHs, substrate preparations, temperature, inhibitors and metal ions on LOX activity were evaluated at three conditions. The enzyme was most active with H...