In this Paper we present the hierarchical designs methodologies for integrated Circuits (IC) for a Very Large Scale Integration (VLSI) using free CAD tools Alliance. Alliance allow us to capture our digital designs through a hardware description language VHDL. Unlike the small digital systems which complete description can be included in a single VHDL file, the ICs designs for a medium and larg...

The design complexity and increasing speed of very-large-scale integration (VLSI) chips implies a significant increase in the power consumption. So, many different design approaches have been developed by researchers to reduce the power. This paper presents an algorithmic technique based on hybridizing Symbolic Manipulation Techniques based on BDDs with more traditional explicit solving algorit...

Design rule checking (DRC) is an important step in VLSI design in which the widths and spacings of design features in a VLSI circuit layout are checked against the design rules of a particular fabrication process. In the past, some efforts to build hardware accelerators for DRC have been proposed, but these efforts were hobbled by the fact that it is often impractical to build a different rule-...

CMOS technology has continuously scaled into deep sub-micron regime. With CMOS scaling, many complex design issues arise. The challenges include, but not limited to, the increasing of interconnect delay and power, exponential growth of leakage power, and rapid growth of design complexity. These challenges motivate us to design new CAD algorithms to reduce power consumption (both leakage power a...

A new short circuit power model for complex CMOS gates, " in Proc. An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation on CAD, " IEEE Trans. An analytical model for current, delay, and power analysis of submicron CMOS logic circuits, " IEEE Trans. Channel width tapering of serially connected MOSFET's with emphasis on power dissipation, " IEEE Tran...

One-dimensional homotopic compaction is defined as; In a given routable layout, a layout of minimum width is reachable by operations that can move each module horizontally as a unit, also deform lines maintaining their connections and maintain their routability. This paper exploits the nature of parallelism of this problem and introduces an efficient cellular automata algorithm for homotopic co...

In this paper, we describe a parametrized sorting system for a large set of k-bit elements. The structure of the system is independent from the problem size (the number of elements to be sorted) and the type of the sorting set (for example, a set of k-b i t n umbers, an alphabetical list of k-bit words etc.), as well as from the ordering relation deened on the set of the elements (such as ascen...

In modern high performance integrated circuits, maximum of the total active mode energy is consumed due to leakage current. SRAM cell array is main source of leakage current since majority of transistor are utilized for on-chip memory in today high performance microprocessor and system on chip designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply volt...

Today’s Integrated Circuit (IC) architects depend on Electronic Design Automation (EDA) software to conquer the overwhelming complexity of Very Large Scale Integrated (VLSI) designs. As the complexity of IC chips is still fast increasing, it is critical to maintain the momentum towards growing productivity of EDA tools. On the other hand, singlecore Central Processing Unit (CPU) performance is ...

Nous présentons un ensemble de travaux pratiques qui seront dispensés au sein du Master EEA - Électronique Embarquée à l’université Lorraine dans le cadre des modules Modélisation SystemC et Conception VLSI. Ces TP sont destinés initier les étudiants la compréhension, modélisation conception réseaux neurones convolutifs langages description matériel niveau RTL (VHDL, module VLSI) langage haut (...